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BACKGROUND OF THE INVENTION
This invention relates to an electrosurgical generator, and more
specifically to an electrosurgical generator which selectively generates a
variety of coagulate signals and cutting signals.
Past electrosurgical generators normally produced a variety of signals and
have controls to adjust signal strength and other parameters of operation.
One problem with past electrosurgical generators has been that the
multiplicity of controls impaired the treating physician's ability to
switch rapidly from one signal mode to another, a particularly crucial
problem when medical exigencies require rapid response. Since such
controls are most useful when placed within easy reach of operating
personnel, isolation from shock hazard is very important, not only for the
patient, but also for the physician. Past generators have typically used
only a single isolation transformer with the side taps coupled through
blocking capacitors to the output terminal. This isolation scheme has
often proved inadequate to eliminate the danger of electric shock. For a
discussion of the prior art of isolation, see the U.S. Pat. No. 4,094,320
assigned to Valleylab, Inc.
Furthermore, past electrosurgical generators have produced a simultaneous
cutting and coagulating effect, known in the art as a blend signal, by
literally blending a cut signal and a coagulate signal. Since
significantly different signal levels are required to produce comparable
levels of effectiveness between these two signals, past generators have
included complex hardware to accomplish an effective literal blending.
See, for example, the U.S. Pat. No. 4,154,240.
Incisions created by electrosurgical generators are based on the creation
of an ionization path between the closely-spaced electrodes of the
electrosurgical scalpel. Past generators have normally utilized high power
output levels to maintain an active ionization path, which not only
required a massive power supply and generating hardware, but also
dissipated waste heat along the incision, and disrupted tissue
unnecessarily. A typical prior art electrosurgical incision of the skin
would therefore cause a continuous explosive sputtering of the fat layer
directly underneath the skin, and the skin incision would heal slowly to
produce substantial scar tissue. Users of prior art electrosurgical
generators would typically make an initial incision through the skin and
fat layer with the traditional knife scalpel in order to avoid this
problem.
Some prior art generators have featured a constant-current output amplifier
in order to produce a uniform electrosurgical effect over a fairly broad
range of tissue impedance. See U.S. Pat. No. 3,601,126 for an output
feedback system to maintain constant output levels. Where differing signal
frequencies were used as the basis for different generator output modes,
the change in frequency would change the output impedance of the
amplifier. In this regard see U.S. Pat. No. 3,699,967, assigned to
Valleylab, Inc. Thus, past generators with constant-current output
amplifiers were in fact limited to a fairly narrow range of tissue types
and incision techniques.
SUMMARY OF THE INVENTION
In accordance with the present invention there is provided a fixed high
frequency oscillator, a variable frequency divider, a low frequency
oscillator or timer, means for interrupting the fixed high frequency
oscillator output signal using both the frequency divider and the timer
and means for altering the interruption pattern of the frequency divider
in order to produce a pure cut, blend, fulgurate or desiccate output
signal. One pulse of each output pulse group is an extremely narrow
voltage spike which re-establishes the ionization path through local
tissues anomalies such as gristle in normal nonhomogenous human tissue.
The high ratio of peak power to RMS power in this pulse spike allows
re-ionization without harmful dissipation of excess power through tissue.
The remaining pulses of each output pulse group are of uniform peak
voltage substantially lower than the peak of the previous voltage spike
and the output pulse group as a whole produces an incision using minimal
electrical power and which will heal rapidly with minimal scar tissue.
Repeated re-ionization using the voltage spike makes the present invention
especially useful for initial incisions through skin and fat layers
without sputtering, which avoids the need for a starter incision made by a
knife scalpel.
Because the four modes of operation of the present invention are based on
the use of a single fixed high frequency oscillator to generate an output
signal, the impedance of the output amplifier is not significantly
affected by variation in output frequency. The present invention is
therefore more useful than the prior art over a wide variety of
application parameters including electrode types, human tissue impedance
variation, and differences in incision motions used by treating
physicians. Users find that less practice is required with the present
invention than with the prior art in order to learn an effective incision
stroke.
The present invention also provides isolation from shock hazard at a
plurality of points in the generator. The hand-held control switches are
isolated from the command control using a small dedicated power supply and
an opto-isolator. The output of the interrupt means is coupled to the
input of the main amplifier through a blocking capacitor to block spurious
D.C. current from passing to the patient, and various stages of the output
amplifier are isolated from one another and from the output terminals by
isolation transformers.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a partial block diagram and partial circuit diagram showing one
example of the electrosurgical generator according to this invention;
FIG. 2 is a circuit diagram showing the command control 103 of FIG. 1;
FIG. 3 is a circuit diagram of the mode control 105 and output control
amplifier 107, 109, 111, and 113 of FIG. 1;
FIG. 4 is a circuit diagram of the high frequency oscillator 115, timer
117, variable frequency divider 119 and NAND gates 1311 and 1382 of FIG.
1;
FIG. 5 is a circuit diagram of the voltage controlled main amplifier 121 of
FIG. 1;
FIG. 6 is a circuit diagram of a digital display of the output level of the
output control amplifiers of FIG. 3;
FIG. 7 is a diagram of the wave form of the high frequency oscillator 115
and the variable frequency divider 119 of FIG. 1;
FIG. 8 is a circuit diagram of the isolation 101 of FIG. 1;
FIG. 9 is a diagram of the output wave form of the generator in pure cut
mode;
FIG. 10 is a diagram of the output wave form of the electrosurgical
generator in blend mode;
FIG. 11 is a diagram of the output wave form of the electrosurgical
generator in desiccate mode;
FIG. 12 is a diagram of the output wave form of the electrosurgical
generator in fulgurate mode;
FIG. 13 is a circuit diagram for a power supply for the electrosurgical
generator;
FIG. 14 is a circuit diagram for a patient isolation for the
electrosurgical generator; and
FIG. 15 is a circuit diagram for an alternate patient isolation for the
electrosurgical generator.
DETAILED DESCRIPTION OF THE DRAWINGS
The best mode and preferred embodiment of the invention is shown in FIGS. 1
through 6 and 8 and comprises a signal generator circuit generally
indicated at 10 to selectively generate a pure cut signal, a blend signal,
a fulgurate signal, or a desiccate signal. These four modes of operation
are treated as two command groups: the cut command includes the pure cut
and blend modes, while the coagulate command includes the fulgurate and
desiccate modes. The treating physician may continuously select either the
cut command or the coagulate command using the hand switches 510 and 511
or the foot switches 512 and 513. The hand switches, which are most likely
to come into electrical contact with the patient or physician during
normal use, are isolated from the bulk of the electric circuit by
isolation circuit 101. If both the cut and the coagulate commands are
selected simultaneously by the physician, the command control 103 will
shut off all functions until the command ambiguity is resolved. Otherwise,
the command control 103 activates command line 201 if the cut command is
chosen, or command line 202 if the coagulate command is chosen.
The command line thus activated will in turn activate one of the two mode
switches 9901 or 9902 which are part of the mode control 105. Switch 9901
is enabled by the cut command line 201 and allows the operator to choose
between the two cut modes: pure or blend. Switch 9902 is enabled by the
coagulate line 202 and allows the operator to choose between the two
coagulate modes: desiccate or fulgurate. Since only one of the two command
lines are active at any moment, only one of the four mode lines 301, 302,
303, and 304 will be activated by the mode control 105 at any moment.
The active mode line enables one of the four output control amplifiers 107,
109, 111, and 113. These amplifiers produce a voltage controlling the
output gain of the main amplifier 200. Amplifiers 107 and 109 control the
cut modes output levels and are controlled by potentiometer 3906.
Amplifiers 111 and 113 control the output level for the two coagulate
functions and are controlled by potentiometer 3907.
Activation of either of the two command lines 201 or 202 will cause NAND
gate 1311 to activate the fixed high frequency oscillator 115 and the
timer 117. The output of fixed high frequency oscillator 115, preferably
450 KHz, passes through NAND gate 1382 to reach the main amplifier 200.
The variable frequency divider 119 produces the primary modulation of the
high frequency signal by counting the output pulses of the fixed high
frequency oscillator 115 and periodically interrupting the output of NAND
gate 1382. FIG. 7 shows the interruption pattern T.sub.1 +T.sub.2 of high
frequency oscillator output 90 produced by divider 119. The uninterrupted
period T.sub.1 of NAND gate 1382 output determines the duration of the
output pulse group and is chosen by the activated mode line, and the
repetition period of T.sub.1 +T.sub.2 is a fixed multiple of the
wavelength of high frequency oscillator output 90. The resulting output
waveform of NAND gate 1382 is shown at 92.
The output of NAND gate 1382 is also interrupted periodically by timer 117
to produce a secondary modulation of the high frequency signal. The timer
operates at a fixed frequency much lower than that of the fixed high
frequency oscillator 115 and the variable frequency divider 119,
preferably 5 KHz.
The output of NAND gate 1382 is fed to the input of main amplifier 200. As
previously stated the output level of the main amplifier 200 is set by the
output of the activated output control amplifier. The main amplifier
output draws current from the D.C. voltage source 123 through the output
isolation 800. The treating physician may choose between bipolar and
monopolar output configuration by making appropriate connections between
the patient electrodes and the output isolation 800.
FIG. 8 illustrates an isolation circuit 101 which isolates and reduces RF
leakage between hand-held command switches 510, 511 and the command
control 103. The isolation circuit consists of an audio frequency
oscillator, preferably running at 23 KHz, which pulses transistor 2401.
The oscillator is formed by integrated circuit 1411, typically a type 556
timer with 12 volts supplied to pins 4 and 14. Resistor 3402 connects pins
14 and 1; resistor 3403 connects pin 1 to pins 2 and 6. Capacitor 4402
connects pin 6 to ground, capacitor 4403 connects pin 3 to ground, and pin
7 is grounded directly.
The output of integrated circuit 1411 passes from pin 5 through resistor
3404 to the base of transistor 2401. Resistor 3405 couples the emitter of
transistor 2401 to ground, and the collector of transistor 2401 is coupled
to the 12 volt supply through capacitor 4404, resistor 3406, and the
primary winding of transformer 5401 in parallel. As the oscillator pulses
transistor 2401, current is alternately blocked or drawn through the
primary winding of transformer 5401. The cathodes of diodes 6402 and 6403
are coupled to te side taps of the secondary winding of transformer 5401.
Capacitor 4409 couples the center tap of the secondary winding of
transformer 5401 to the anodes of diodes 6402 and 6403. The center tap is
further coupled directly to the common line connecting hand switches 510
and 511. Capacitor 4405 couples the center tap of the secondary winding of
transformer 5401 to switch 510 and resistor 3412. Switch 510 is connected
through resistor 3412 to pin 1 of opto-isolator 1421. Diode 6404 is
connected between pins 1 and 2 of opto-isolator 1421; pin 2 is also
connected to anodes of diodes 6402 and 6403.
Similarly, capacitor 4406 couples the center tap of the secondary winding
of transformer 5401 to switch 511 and resistor 3413. Switch 511 is
connected through resistor 3413 to pin 1 of opto-isolator 1422; pin 1 is
also connected through diode 6405 to pin 2, to pin 2 of opto-isolator 1421
and to the anodes of diodes 6402 and 6403.
Opto-isolator 1421 is grounded to the output circuit ground at pin 4. Pin 5
is the output for switch 510, and is connected through resistor 3414 to a
12 volt supply, through resistor 3417 to line 525, and through resistor
3417 and capacitor 4411 in series to ground. Pin 6 is coupled through
capacitor 4421 to ground. Likewise, opto-isolator 1422 is grounded to the
output circuit ground at pin 4. Pin 5 is the output for switch 511, and is
connected through resistor 3415 to a 12 volt supply, through resistor 3416
to line 526, and through resistor 3416 and capacitor 4410 to ground. Pin 6
is coupled through capacitor 4420 to ground.
The secondary voltage of the transformer is full wave rectified and
filtered to a D.C. voltage by diodes 6402 and 6403 and capacitor 4409.
Resistors 3412 and 3413 limit the small amount of D.C. current supplied to
the hand switches and the input diodes of opto-isolators 1421 and 1422.
For example, when the cut command group is activated by closing switch
510, current flows through resistor 3412 and pins 1 and 2 of opto-isolator
1421 which causes the output of the opto-isolator 1421 to go low.
Referring now to FIG. 2, the inputs of inverters 1431 and 1432 are
connected to the hand switches 510 and 511, respectively, via isolation
101 and lines 525 and 526 respectively. The input of inverter 1433 is
coupled through switch 512 and capacitor 4407 in parallel to ground, and
through resistor 3407 to a 12 volt supply. Likewise, the input of inverter
1434 is coupled through switch 513 and capacitor 4408 in parallel to
ground and through resistor 3408 to a 12 volt supply. Therefore, the
inputs of inverters 1433 and 1434 will remain at high value unless a
switch is closed, at which time the respective inverter input will go low
and its output will go high.
The outputs of inverters 1431 and 1433 are coupled directly to the inputs
of NOR gate 1441. Therefore, when either or both of switches 510 and 512
are opened, the output of NOR gate 1441 will be low. The outputs of
inverters 1432 and 1434 are coupled directly to the inputs of NOR gate
1444. Therefore, when either or both of switches 511 and 512 are opened,
the output of NOR gate 1444 will be low.
The outputs of inverters 1431 and 1432 are also coupled to the inputs of
NOR gate 1442. When either or both of switches 510 and 511 are closed, the
output of NOR gate 1442 will go low. The output of inverters 1433 and 1434
are coupled to the inputs of NOR gate 1443. When either or both of
switches 510 and 511 are opened, the output of NOR gate 1443 will go low.
The outputs of NOR gates 1442 and 1443 are coupled to the inputs of NOR
gate 1451, and the outputs of NOR gates 1441 and 1444 are coupled to the
inputs of NOR gate 1452. The outputs of NOR gates 1451 and 1452 are
coupled to the inputs of NOR gate 1453.
The cut command may be indicated by closing either of switches 510 or 512,
and the coagulate command may be indicated by closing either of switches
511 or 513. When any two switches are closed indicating conflicting
operation modes at the same time, the output of NOR gate 1453 will go low.
The output of NOR gate 1441 is coupled through inverter 1435 to one input
of NAND gate 1461. The output of NOR gate 1453 is connected to another
input of NAND gate 1461, and the output of thermostat 9903 is coupled to a
third input of NAND gate 1461. Thus, when the output of inverter 1435 is
high, indicating cut command, and the output of NOR gate 1453 is high,
indicating no conflicting command, and the out-put of thermostat 9903 is
high, indicating no heat overload, then the output of NAND gate 1461 will
be low activating the command line 201 through switch 9907. If the output
of NOR gate 1453 goes low or the output of thermostat 9903 goes low, the
output of NAND gate 1461 goes high, deactivating command line 201.
The output of NAND gate 1461 is also coupled through inverter 1471 and
resistor 3410 in series to the base of transistor 2403. The emitter of
transistor 2403 is grounded and the collector of transistor 2403 is
coupled through lamp 7903 to a 12 volt supply. When NAND gate 1461
activates command line 201, the base of transistor 2403 goes high, drawing
current through lamp 7903 which lights to indicate cut command group
operation to the treating physician.
Similarly, the output of NOR gate 1444 is coupled through inverter 1436 to
one input of NAND gate 1462. The output of NOR gate 1453 is connected to
another input of NAND gate 1462, and the output of thermostat 9903 is
coupled to a third input of NAND gate 1462. When the output of inverter
1436 is high, indicating coagulate command, the output of NOR gate 1453 is
high, indicating no conflicting command, and the output of thermostat 9903
is high, indicating no heat overload, then the output of NAND gate 1462
will be low, activating the command line 202 through switch 9908. If the
output of NOR gate 1453 goes low or the output of thermostat 9903 goes
low, the output of NAND gate 1462 goes high, deactivating command line
202.
The output of NAND gate 1462 is also coupled through inverter 1472 and
resistor 3411 in series to the base of transistor 2404. The emitter of
transistor 2404 is grounded and the collector of transistor 2404 is
coupled through lamp 7904 to a 12 volt supply. When NAND gate 1462
activates command line 202, the base of transistor 2404 goes high, drawing
current through lamp 7904 which lights to indicate coagulate command group
operation to the treating physician.
The output of NOR gate 1453 and thermostat 9903 are also coupled to the
inputs of NAND gate 1481. The output of NAND gate 1481 is connected
through inverters 1482, 1473, and resistor 3420 in series to the base of
transistor 2402. The emitter of transistor 2402 is grounded, and the
collector of transistor 2402 is connected through lamp 7902 to a 12 volt
supply. If either thermostat 9903 or the output of NOR gate 1453 goes low,
then the base of transistor 2402 will go high and current will glow
through lamp 7902, indicating to the treating physician that the generator
has automatically ceased operation.
The outputs of NAND gate 1461 and 1462 and of inverter 1482 are coupled to
the inputs of NAND gate 1483. The output of NAND gate 1483 is connected to
pin 10 of integrated circuit 1412. If either command line 201 or 202 is
activated, or if the generator is automatically shut down, the output of
NAND gate 1483 goes high, activating an oscillator formed by integrated
circuit 1412 and associated passive elements. Pin 14 of integrated circuit
1412 is connected to a 12 volt supply, and pin 14 is also connected
through resistor 3418 to pin 13. Pin 13 is connected through resistor 3419
to pins 8 and 12. Pin 7 is grounded, and is connected through capacitor
4413 to pin 11. Pin 7 is also coupled through capacitor 4412 to pins 8 and
12. The oscillator output is pin 9 of integrated circuit 1412, which is
coupled to the input of binary counter 1496.
Binary counter 1496 divides the output frequency of the oscillator by three
different fixed factors. Each of three counter outputs are coupled to an
input of NOR gates 1491, 1492, and 1493 respectively. The output of
inverter 1482 is coupled to the second input of NOR gate 1491, so that
when NOR gate 1453 or thermostat 9903 cause a shutdown, the output of NOR
gate 1491 will be the inverse of the associated input from the counter
1496. Likewise, command line 201 is coupled to the second input of NOR
gate 1492, so that when command line 201 is activated, the output of NOR
gate 1492 will be the inverse of the associated input from the counter
1496. Further, command line 202 is coupled to the second input of NOR gate
1493, so that when command line 202 is activated, the output of NOR gate
1493 will be the inverse of the associated input from the counter 1496.
The output of NOR gates 1491, 1492, and 1493 are coupled to the inputs of
NOR gate 1494. Thus, the output of NOR gate 1494 will be a frequency
corresponding to the status of the generator: either cut command,
coagulate command, or automatic shutdown. If no command is selected, the
output of NOR gate 1494 is fixed at high value.
The output of NOR gate 1494 is coupled through inverter 1495, resistor 3412
and potentiometer 3908 to ground. The wiper of potentiometer 3908 is
connected through capacitor 4415 to one input of operational amplifier
1497, which input is connected to ground through capacitor 4416. Capacitor
4415 is also coupled to the second input of operational amplifier 1497
through capacitor 4414. The output of operational amplifier 1497 is
coupled to ground through capacitor 4417 and loudspeaker 9906 in series.
Therefore, the loudspeaker 9906 produces a tone for audible indication of
generator status. The volume of the tone is varied by adjustment of
potentiometer 3908.
FIG. 3 shows the mode control 105 and amplifiers 107, 109, 111, and 113.
Command line 201 is coupled to the input of inverter 1611. Additionally, a
12 volt source is connected through resistor 3604 to the input of inverter
1611, so that the input of inverter 1611 is normally high value. The
output of inverter 1611 is coupled to the input of NAND gate 1621, and to
the input of NAND gate 1622.
When command line 201 is activated, the treating physician may select
between the pure or blend modes by double pole/double throw switch 9901.
Both wipers of switch 9901 are grounded. A 12 volt supply is connected
through lamps 7905 and 7906 to the respective contacts for one wiper of
switch 9901. Of the remaining two contacts of the second wiper of switch
9901, one contact is coupled to the input of inverter 1614, and the other
contact is unconnected. A 12 volt supply is also coupled through resistor
3605 to the input of inverter 1614 and from that point through capacitor
4603 to ground. The output of inverter 1614 is coupled to an input of NAND
gate 1621 and also coupled to the input of inverter 1613. The output of
inverter 1613 is coupled to an input of NAND gate 1622.
Therefore, when command line 201 is activated (i.e., low value) and one
wiper of switch 9901 makes contact with lamp 7905, the output of NAND gate
1621 is low and the output of NAND gate 1622 is high. Also, current is
drawn through lamp 7905, indicating by light that the pure mode of
operation has been selected. When command line 201 is low and switch 9901
makes contact with lamp 7906, the output of NAND gate 1621 is high and the
output of NAND gate 1622 is low. Also, a lamp 7906 is lit, giving a visual
indication that the blend mode of operation has been selected.
Similarly, when command line 202 is activated, the treating physician may
select between the desiccate of fulgurate operations by double pole/double
throw switch 9902. Both wipers of switch 9902 are grounded. A 12 volt
supply is connected through lamps 7907 and 7908 to the respective contacts
for one wiper of switch 9902. Of the remaining two contacts of the other
wiper of switch 9902, one contact is coupled to the input of inverter
1616, and other contact is unconnected. A 12 volt supply is also coupled
through resistor 3606 to the input of inverter 1616 and from that point
through capacitor 4604 to ground. The output of inverter 1616 is coupled
to the input of NAND gate 1624 and also coupled to the input of inverter
1615. The output of inverter 1615 is coupled to the input of NAND gate
1623.
Therefore, when command line 202 is activated (i.e., low value) and one
wiper of switch 9902 makes contact with lamp 7907, the output of NAND gate
1623 is low and the output of NAND gate 1624 is high. Also, current is
drawn through lamp 7907, indicating by light that the desiccate mode of
operation has been selected. When command line 202 is low and switch 9901
makes contact with lamp 7908, the output of NAND gate 1623 is high and the
output of NAND gate 1624 is low. Also, lamp 7908 is lit, giving a visual
indication that the fulgurate mode of operation has been selected.
A typical amplifier 109 may be described as follows: The output of NAND
gate 1622 is connected to the input of inverter 1632, and the output of
inverter 1632 is connected to the anode of diode 6612. The output of NAND
gate 1622 is also coupled to the input of inverter 1642, which supplies
base current to the two transistors associated with the blend mode
amplifier 109. The output of inverter of inverter 1642 is coupled through
resistor 3612 to the base of transistor 2613. Transistors 2611, 2622, and
2613 operate in switching mode in this circuit; that is, when the output
of inverter 1642 is high and current is supplied through the base
resistors of the transistors, the collector and emitter of each transistor
are shorted. When no base current is supplied, the collector and emitter
are disconnected. The output of inverter 1642 also drives mode line 302.
The cathode of diode 6612 is connected through resistor 3608 to one side of
potentiometer 3906. The other side of potentiometer 3906 is connected to
resistor 3624 and capacitor 4607 in parallel. Capacitor 4607 is connected
to ground. Resistor 3624 is coupled to the collector of transistor 2622.
The emitter of transistor 2622 is connected to ground.
The wiper of potentiometer 3906 is connected through capacitor 4605 to
ground, and the wiper is also connected to the collector of transistor
2613. The emitter of transistor 2613 is connected through resistor 3628 to
the positive input of operational amplifier 1652.
Therefore, when the output of NAND gate 1622 is low indicating the blend
mode of operation, the output of inverter 1632 is high. This voltage is
connected to the potentiometer 3906. The voltage across potentiometer 3906
is established by the difference between the voltage supplied by inverter
1632 and the voltage across potentiometer 3624 and transistor 2622. In
effect, potentiometer 3624 sets the minimum value of the output power
range which may be controlled by potentiometer 3906.
The output of operational amplifier 1652 is connected through potentiometer
3636 and resistor 3632 to the negative input of operational amplifier
1652. This feedback loop establishes the gain of the operational amplifier
configuration so that in effect the variable resistor 3636 establishes the
maximum limit of the output power range controlled by the setting of
potentiometer 3906. The output of operational amplifier 1652 is also
connected through diode 6604 to voltage controlled main amplifier 800 via
transmission line 502. The output of operational amplifier 1652 easily
overcomes the forward bias voltage of diode 6604, but the reverse bias
voltage of diode 6604 prevents any of the other three amplifiers which are
coupled to line 502 from creating undesired feedback in operational
amplifier 1652.
The amplifiers for the three remaining modes of operation of the invention
operate in similar fashion.
FIG. 4 shows the high frequency oscillator 115, the variable frequency
divider 119, the low frequency oscillator 117 and NAND gates 1311 and
1382.
Command line 201 is connected to one input of NAND gate 1311. A 12 volt
supply is also connected through resistor 3306 to that input of NAND gate
1311, so that when command line 201 is not activated, the input will be
high. Command line 202 is connected to another input of NAND gate 1311,
and the 12 volt supply is also connected through resistor 3305 to this
second input of NAND gate 1311 so that when command line 202 is not
activated, the second output will also be high. However, if either command
line is activated, the output of NAND gate 1311 will go high, activating
the fixed high frequency oscillator 115 and the low frequency oscillator
117.
The output of NAND gate 1311 is connected to one input of NAND gate 1312.
The output of NAND gate 1312 is coupled to the input of inverter 1313. The
output of inverter 1313 is coupled through capacitor 4302 and resistor
3302 in series to the second input of NAND gate 1312. The output of NAND
gate 1312 is also coupled through resistor 3304 and potentiometer 3303 in
series to the resistor 3302. These elements comprise the fixed high
frequency oscillator 115, the frequency of which be initially calibrated
and set by adjustment of potentiometer 3303. The output of the oscillator
is the output of the inverter 1313, which is coupled to the input of
inverter 1314. The output of inverter 1314 is coupled to the counter input
of integrated circuit 1331 and to one input of NAND gate 1382.
The output of NAND gate 1311 is also coupled to pin 4 of integrated circuit
1321. This integrated circuit is preferably a type 555 timer. A 12 volt
supply is connected directly to pin 8 and through resistor 3308 to pin 7.
Pin 7 is connected through resistor 3309 and diode 6302 in parallel to
pins 6 and 2. Pin 2 is connected through capacitor 4304 to ground, pin 1
is connected directly to ground, and pin 5 is connected through capacitor
4303 to ground. Integrated circuit 1321 and associated elements comprise
the low-frequency oscillator 117. The output of the low frequency
oscillator is pin 3, which is connected to a second input of NAND gate
1382.
Integrated circuit 1331 is preferably a binary counter type 4040. The
status of the output pins of integrated circuit 1331 presents a binary
representation of the number of pulses of fixed high frequency oscillator
115. The three NAND gates, 1342, 1351, and 1352 vary the counter's
function according to the mode selected by the operator, as represented by
the status of the three mode lines 302, 303, and 304. The input of
inverter 1399 is connected to pin 3 of integrated circuit 1331. The inputs
of NAND gate 1342 are connected to the mode line 302 and pins 6, 7, and 9
of integrated circuit 1331. The inputs of NAND gate 1351 are connected to
mode line 303, to pins 7 and 9, and to the output of inverter 1399. The
inputs of NAND gate 1352 are connected to mode line 304, to pin 9 (twice)
and to the output of inverter 1399. The output of each of these three NAND
gates are connected to the input of NAND gate 1362, and the output of NAND
gate 1362 is connected to the input of inverter 1377.
NAND gates 1378 and 1379 are configured to act as a set-reset flipflop. The
output of NAND gate 1378 is coupled to one input of NAND gate 1379, and
the output of NAND gate 1379 is coupled to one input of NAND gate 1378.
The output of inverter 1377 is connected to the second input of NAND gate
1379 and the output of NAND gate 1381 is connected to the second input of
NAND gate 1378. The output of NAND gate 1378 is also connected to a third
output of NAND gate 1382.
Pins 3, 7, and 9 of integrated circuit 1331 are connected to three inputs
of NAND gate 1361. The fourth input of NAND gate 1361 is coupled through
resistor 3310 to a 12 volt supply, and through capacitor 4305 to ground.
The output of NAND gate 1361 is connector to the input of inverter 1391.
The output of inverter 1391 is connected to one input of NAND gate 1381
and the output of inverter 1314 is connected to the | | |
