A loop control system for digital processing apparatus. A dedicated storage register and associated counting register are provided for receiving a starting value representing a number of passes through a program loop. An iteration circuit is provided for receiving the value in the counting register, iterating it, and storing the new value in the same counting register with each successive pass through the loop. A detector is provided for comparing the output of the iteration circuit to a predetermined value and providing a completion signal when the new value and the ending value have a predetermined relative relationship. Control logic is provided for causing the value in the storage register to be transferred into the counting register upon the occurrence of an output signal from the detector circuit. A plurality of pairs of storage and counting registers may be provided for keeping track of the number of iterations of nested loops.

A sequencer executes instructions based on a function clock signal to perform I/O functions in a serial peripheral interface based on a source clock signal. The function clock signal has a frequency of two times the frequency of the source clock signal. A function clock generator generates the function clock signal and operatively selects the instruction to be decoded. The instruction selectively forces the frequency of the function clock signal to be equal to the frequency of the source clock signal during the duration of that function clock signal during which the predetermined instruction is decoded to execute a single instruction during the source clock signal, to advantageously repeat the execution of the instruction without consuming clock cycles.

A data processing system, for processing programs in the form of networks of connected processing elements each relating to an arithmetic or logical operation, includes a memory for storing code representations of the processing elements and process data, processing apparatus including address computation circuitry for generating addresses for the memory and arithmetic and logic circuitry for processing the process data. A finite state machine receives the code representations of the processing elements and generates control signals for controlling the address computation circuitry, arithmetic and logic circuitry and memory in response to the nature of the processing element.

Several I/O channel processes time share a data pipeline processor. For each stage of the pipeline, there is a control memory and means for shifting an address from memory to memory as a process in the pipeline proceeds from stage to stage. The number of processes is greater than the number of pipeline stages, and storage is provided for the data and for the addresses while a process is out of the pipeline, waiting to be re-entered for a next pass. A storage array for holding the addresses is arranged to hold addresses for four activity levels for each process. While an address is held in the array it can be modified for the next pass through the pipeline or the process can be switched from a lower priority level activity to a higher level activity.

A specialized apparatus and method for providing fast programmed I/O for transferring information in a multi-processor environment which includes a CPU, and a memory coupled to an I/O port across an internal data bus. Multiple bytes of data are transferred in successive processing cycles to the I/O port from the memory, or from the I/O to the memory by first determining the upper limit for the number of bytes that are going to be transferred. This number and the memory start address are then stored in CPU registers. The I/O module is then checked by the CPU to see if a data byte is available from an external device. If a data byte is available, the I/O module is instructed to place the data byte on the bus for storage within the memory at the start address. The address is then incremented and the count is decremented. The above procedure is repeated until the count drops to zero, after which time the next instruction is fetched.