A single-chip microcomputer comprises a processor incorporating a computation process control unit and an operation execution unit. The microcomputer further comprises a memory unit, an interface, a buffer storage cell, and a unit to control exchange of information transmitted through a system line. All these units and the processor with its computation process control unit and operation excution unit are interconnected by a bidirectional bus. The processor also includes a buffer storage cell, a processor information exchange control unit, and an address comparator, which are all interconnected. The single-chip microcomputer further contains a bus arbiter and a system line arbiter which are connected to the unit to control exchange of information transmitted through the system line. Finally, the microcomputer includes a system line address comparator connected to the processor and buffer storage cell. The single-chip microcomputer according to the invention can be combined into a system with a common memory field.

An image output apparatus comprises an image information supply unit, an output unit for causing any image information to be put out from the supply unit, a designating device for designating an image to be put out from the image information of the supply unit, a command device for commanding a change of the designated image, and a control device whereby, when a designated image change command is given before the outputting of a previously designated image is completed, the outputting of the previously designated image is stopped and the outputting of a newly designated image is started.

A word processing system having foreground and background modes of operation, wherein the full capability of the word processing system is available to both the foreground mode and background mode. The system comprises a display, a processor system for processing information and controlling the display and having foreground/background capability so that two jobs may run concurrently, a first buffer for storing information relating to a first job being run in the foreground mode, a second buffer for storing information relating to a second job being run in the background mode, and an input device for entering textual and command information into the system. Information in the first buffer is displayed on the display. Upon receipt of a command from the input device the processor enters the background mode and interchanges the buffers so that information relating to the background job is displayed, and upon receipt of a second, subsequent command, the processor returns to the foreground mode and again interchanges the buffers. In a preferred embodiment the processor system comprises first and second processors interconnected so that either may access the memory of the other.

An address designating method of a memory is performed by dividing the addresses of the memory to row addresses and column addresses. The writing of data in the memory is performed by the following steps. Namely, while the row addressing is maintained in a predetermined value (for example, 7d+1), the column addressing is incremented one by one. When the column addressing reaches 3, the row addressing is decremented by 4d+1. Each time the row addressing is decremented by d, the column addressing is decremented one by one in accord therewith. The reading of the data from the memory is performed by the following steps. Namely, each time the row addressing is incremented by d, the column addressing is also incremented one by one in accord therewith. When the column addressing reaches 3, the row addressing is decremented by 3d+1. With the row addressing kept in 0, the column addressing is decremented one by one.

A controller for use with a magnetic tape drive which has a plurality of buffer memories for temporarily storing data that is passed between the tape drive and a host computer system. Temporary storage of data within the tape controller allows data to be rewritten on the tape if the initial writing is faulty and allows data read from the tape to be reconstructed if the data has been erroneously recorded. Transfer of information into and out of the buffer circuits is controlled by two independent direct memory access circuits--one circuit transfers data between the host computer system and the buffer memories and the other circuit transfer data between the buffer memories and the tape drive. Each of the direct memory access circuits operates independently of the other, however, both circuits are coordinated by a central processing unit which communicates with the direct memory access units by means of an interrupt arrangement. The controller also contains a serial input/output unit which allows the controller to format and decode a data format that allows synchronous decoding of the data which in turn permits "on the fly" error correction.