A test pattern generator includes: an algorithmic pattern generator, a sequential pattern generator, a selector for selecting one of an algorithmic pattern and a sequential pattern for use with a specified pin of an object device to be tested; and a pattern controller for controlling the selector, whereby data to be supplied to a pin or pin block can be assigned in real time by the pattern controller.

Apparatus consisting of combinations of interconnected logic elements for generating preselected sequences of addresses for the listing of a matrix memory as a function of preset constants and variable timing impulses, wherein there are first and second X and Y address generators with controlled selection means for selecting the first or the second of the X and Y address pairs, each of the address generators being settably controllable to generate a preselected sequence of addresses in ascending or descending order, with settable increments within the sequence, settable masking, and settable displacements from a fixed reference origin.

A technique for configuring improved circuit for generating an output sequence of values such as an output sequence used to test memory components or logic circuits. The inventive method is based on the fact that a factorially produced output sequence of values can be broken or divided into partial sequences and factors which may consist of either a single constant or a single mathematically definable term can be defined there from. The partial sequences may be combined by a multiplexor to form the output sequence. This permits a simple, inexpensive circuit for fast interleaving or pulse sequences to be designed. This can be accomplished by analyzing the desired output sequence of values to be created and arranging this output sequence in partial sequences determined by their periodicity. The circuit designed by this approach needs only a single program storage means to control any number of processes, each of which contains only a single respective value and that these processes need be only a simple arithmetic and logic units (ALUs).

A multi-way interleave-type semiconductor device testing apparatus is provided, which is capable of testing an IC under test in either case that the latency (the number of delay cycles) N of the IC under test is an odd number or an even number. In each of plural test circuit units (4-1 and 4-2) is provided a clock control circuit (23) comprising an adder for adding up the test period Tr of the IC tester and a clock setting value Tc, and a selector (22) for selecting the output from the adder or the clock setting value Tc to output the selected one. The latency is set in a delay setting register (5) which supplies to the selector a binary number "0" when the latency is an even number and a binary number "1" when the latency is an odd number. The selector outputs the clock setting value in case of "0" and outputs the sum of the test period and the clock setting value in case of "1", so that a clock generator (7) outputs the period signal of the test circuit unit at a timing corresponding to the input signal. In a pattern delay circuit (6) is set a delay time obtained by multiplication of the period of the period signal by a decimal number supplied from the delay setting register, thereby to delay an expected value signal EXP to supply it to a logical comparator (9).

A high speed pattern generator includes a programmable counter, n pattern generating circuits, a multiplexer and a control memory. The programmable counter divides a frequency of a system clock signal by n (n.gtoreq.2) to thereby generate a clock signal having a frequency of 1/n of the frequency of the system clock and a select signal representative of a count output of said programmable counter. The n pattern generating circuits operate at a frequency determined by the clock signal and produce a pattern signal as a function. A multiplexer converts patterns generated by the n pattern generating circuits into a time-serial pattern in response to the select signal for sequentially selecting outputs of the n pattern generating circuits to thereby output a fast pattern. A control memory which operates at a frequency determined by the clock signal produces a control signal to periodically switch a frequency division ratio of the programmable counter between a plurality of ratios. When the frequency division ratio is changed, generation of any dummy pattern can be suppressed.