An integrated circuit memory with additional circuitry added so that the integrated circuit acts as a counting memory is disclosed. A memory core is included with associated circuitry allowing it to be accessed in the same manner as ordinary random access memory (RAM). A counter is included and is coupled so that it can receive the contents of any location in the memory core. Each address in the memory acts as an individual counter. When a particular memory address is presented indicating that the count at that memory location should be incremented, the contents of that memory location are transferred to the counter, the counter is incremented, and the contents of the counter are then transferred back to the memory location. This process is repeated each time a new address is presented indicating a new event to be recorded. At the end of a series of events, the core memory will contain, at each corresponding memory location, the number of occurrences of the event assigned to that address.

Addressing circuit for a matrix display having shift registers formed by static memories and process for addressing with such a circuit. For a display with p columns, the circuit comprises p register points formed by static memories (M.sub.i), a first series of switches (C.sub.1) placed in front of the register points M.sub.k-1, k being an even number between 1 and p, a second series of switches (C.sub.2) placed in front of the register points M.sub.k and a transfer clock (13) producing a first signal (.phi..sub.1) controlling the first series of switches, in order to ensure the loading of a "1" signal into the register point (M.sub.1) and the transfer of the content of register point M.sub.k to register point M.sub.k+1, and a second signal (.phi..sub.2) controlling the second series of switches for ensuring the transfer of the content of register point M.sub.k-1 to register point M.sub.k.

A unique memory management system for use with a memory device which is common (or shared) with a plurality of user elements utilizing a memory address counter, scratch pad address memory, external memory address inputs and an address multiplexer.

An addressing device for a memory, such as a dynamic memory ROM or RAM, addressable by address words at a predetermined clock-period rate. Each address word is made up of first and second address words composed of least significant and most significant bits of the address word respectively. The first and second address words are multiplexed. The device comprises an adding circuit for incrementing the first address words in terms of a predetermined digital signal carrying words that are synchronous with the first address words and for incrementing the second address word in each address word by unity whenever the first word of the address word has bits all equal to "1", and a shift circuit looped across the adding circuit in order to deliver the first and second multiplexed address words to the memory.

A memory system for a television receiver is disclosed. The memory system contains an array of addressable memory cells, each row of which can contain one line of sampled video signals. The number of rows in the array is greater than the number of lines in a frame. Apparatus is included in the memory system for simultaneously writing more than one line of samples into the memory, for simultaneously reading more than one line of samples from the memory, or for both. Simultaneous access to multiple lines allows the reading and writing of multiple corresponding lines of samples from both the current and the prior frame. The row addresses that are used to store the lines of samples for a frame are not the same for each frame, rather the lines of each new frame are stored in rows with lesser addresses than the rows used for the prior frame. This introduces a backward scrolling of the stored image from frame to frame which avoids overwriting data to be used in time-domain or spatial-domain filtering done directly from memory.