An output buffer used in, for example, a semiconductor memory device, comprises a first transistor connected between a power potential supply terminal and a data output terminal and a second transistor connected between a reference potential supply terminal and the data output terminal. In response to the data stored in a selected memory cell, either one of the first and second transistors is turned ON to change the potential at the data output terminal to a level corresponding to the data at a first rate. The output buffer further comprises a third transistor connected between the gate of the second transistor and the power potential supply terminal. The third transistor is turned ON before the data stored in the selected memory cell is supplied to the output buffer to vary the potential at the data output terminal to the reference potential at a second rate smaller than the first rate.

Data from a latch section for latching the contents in a plurality of memory cells are selectively applied to a data output section through paired output lines. In the data output section, immediately before the data is output, the nodes providing gate inputs to a load transistor and a drive transistor are connected to a signal for driving the output section and become at ground level. The output of the data, which is the same as that produced in the previous cycle, is continued till the start of a cycle in which the data from the latch section is output to the output line pair. At the start of a cycle in which new data is applied from the output line pair, a reset operation is performed.

An output circuit for a memory device has four MOS transistors. A first MOS transistor and a second MOS transistor comprise an output stage of the output circuit, and a control circuit controls the voltages of the gates of the first and the second MOS transistors. A third MOS transistor has its source connected to the gate of the second MOS transistor, and a fourth MOS transistor has its source connected to the gate of the first MOS transistor. When the data which are supplied to the control circuit are changed, the third or the fourth MOS transistor assists the level shift of the gate of the second and the first MOS transistor at the beginning of the level shift. By continuing the level shift, the third or the fourth MOS transistor is turned off. As a result, the source-gate voltage of the third or the fourth MOS transistor becomes lower than its threshold voltage, so that the switching noise or ground noise is reduced.

A sense circuit for use in a semiconductor memory senses an input signal by comparing the input signal with a reference voltage. The sense circuit comprises a sense amplifier having first and second nodes, and first and second transfer gates. The first transfer gate couples the input signal to the first node of the sense amplifier. The second transfer gate couples the reference voltage to the second node of the sense amplifier. A level-shift circuit is provided between the second node of the sense amplifier and the second transfer gate. In response to the voltage level of the input signal latched in the first node, the level-shift circuit shifts the level of the reference voltage latched in the second node of the sense amplifier to a lower level when the input signal is high in voltage level, and shifts it to a higher level when the input signal is low in voltage level.

There is disclosed a data output circuit with a nibble mode function for a dynamic memory. The data output circuit comprises a plurality of data output control circuits provided in correspondence with a plurality of paired data transfer nodes. Each pair of transfer nodes is connected to the corresponding memory array and receives data stored in a designated memory cell of the memory cell.