A logic gate is disclosed employing enhancement mode MESFET gallium arsenide devices which do not require the tight process control necessary in the prior art because two such devices are employed in the gate circuit to mutually compensate for the effects of their equal deviation from nominal threshold voltages.
A logic circuit using depletion-mode field effect switching transistors, wherein, a plurality of logic elements respectively having at least one depletion-mode switching FET are connected in series. The source electrodes of the switching FETs are maintained at a voltage higher by a predetermined voltage than ground potential by the Schottky diode and connected commonly to each other. The switching FETs are connected at the drain electrodes through active loads to a power source terminal supplied with one type of external DC power source voltage. The drain potential of the switching FETs is level-shifted to a predetermined voltage higher than the gate potential of the FETs in the next stage. The FETs are provided between the diodes and ground to prevent the variation in the level shift voltage.
A circuit comprises P-channel and N-channel field effect transistors. A conduction electrode, such as a drain, of one of the transistors is coupled to a conduction electrode of the other transistor. Means are provided for ensuring that the currents in the transistors when changing state, and hence the rise and fall times of an output signal of the transistors, are substantially equal. Preferably, the ensuring means comprises the channel length of the P-channel transistor being smaller than that of the N-channel device. Alternately, either the doping level or the width of the P-channel device can be greater than that of the N-channel device.
A semiconductor logic circuit utilizing level shifting of input transistors away from a reference voltage level but shifting the output toward the reference voltage level to increase noise margin. The input signals may switch both the input transistors and the output transistors.
In integrated circuits the delay of the signal transitions has to lie within specified limits. This delay is partly determined by variations in the manufacturing process (process scatter). To compensate for the effect of this scatter a load capacitance is connected via a switching element to a node which is to be influenced in the integrated circuit. The switching element receives a reference voltage which is dependent on the manufacturing process and is generated by reference source, so that the node capacitance 26 is connected to the node for a longer or shorter time, depending on the process scatter.
This invention discloses a push pull logic circuit which includes a capacitor connected to the output signal lead of the circuit, and also a plurality of diodes, in parallel with the capacitor and connected to the output signal lead.
