A multiprocessor system comprising a plurality of processors and a memory unit which are connected through a common bus whereby each processor communicates with the memory through the bus. Communication among processors is effected by storing in a plurality of memory zones the messages intended for the several processors. The memory zones are each dedicated to one processors, but are accessible to all the processors. The communication among processors is performed by sending a notify signal on the common bus which is identified only by the processor for which it is intended. The notify signal is acknowledged by the notified processor without interrupting its ongoing operation. The notified processor subsequently accesses the memory unit and reads the message in the appropriate memory zone.
In a multiprocessory system comprising a plurality of CPUs interconnected by a common bus, means are provided whereby the CPUs are periodically and cyclically enabled to access the bus. Data transfer from one CPU to another is performed by first storing the data into a main memory connected to the bus, then transferring the data from main memory to the destination CPU when the latter is enabled to utilize the bus and is in a condition to accept the data. Means can also be provided whereby, when data must be immediately transferred from one CPU to another, the sending CPU stores the data in main memory, generates signals whereby the destination CPU is given use of the bus, and generates an interrupt which causes transfer of the stored data into the destination CPU.
In an intermediate storage of a communication switching system, where connection data are stored in connection-specific data sets, the intermediate storage is continuously checked for the presence of data sets. If at least one such data set is present, then this data set is transmitted in a security transmission method to two separate processing units of a data processing system and written into a memory unit. If only one of two processing units acknowledges error-free reception of a data set, then this processing unit is supplied with a control signal by the communication switching system directing it to copy the data set just received into the memory unit of the other processing unit.
A system uses a resource manager class to allow each task to identify itself and establish OLE links. After each task starts, it calls the resource manager register object method in order to register itself with the resource manager. After registration the resource manager controls the OLE communication when any other task needs to communicate with the task. The system provides a new data object built upon the variant data structure supplied with the Microsoft foundation class (MFC) library. This new data structure is called a getset variant, and it encapsulates the identification of the sender of the data, an access key, used to control access between tasks, the OLE dispatch pointer necessary to access the receiver of the data, and a domain identifier which is used for communication across multiple computer systems.
The system according to the invention comprises a central microprocessor and peripheral microprocessors. A direct-access transfer memory is provided for the communication of the processors with one another. The memory is divided into as many distinct, determined zones as there are peripheral processors. The memory is connected to two addressing buses of which the latter serves equally well to address the boxes of the memory by the central microprocessor and to address the zones of the memory allocated to the peripheral microprocessors. The system is particularly well adapted to data transfers between a telephone automatic switch and subscribers' sets.
A CPU of a microprocessor system is modified to post an executed write I/O instruction upon completion of writing by the bus unit. A dedicated memory area is provided for storing a customizable system interrupt service routine, program state data at the time of interruption and an I/O trap indicator indicating the CPU was interrupted during execution of an I/O instruction. The dedicated memory area is normally not mapped as part of the main memory space, thereby keep it inaccessible to the operating system and applications. An unmaskable system supervisor interrupt having higher priority than all other maskable and unmaskable interrupts is added to the CPU interrupts. A RESUME instruction is added to the CPU instructions to provide recovery of the CPU to the state before it was interrupted and continued execution including automatic re-execution of an interrupted I/O instruction. As a result, a system integrator or OEM may provide transparent system level interrupts with automated I/O trap restart that will operate reliably in any operating environment, and be relieved of the heavy burden of managing I/O trap restart.
