An apparatus for reducing signal degradation, propagation delay, and electromagnetic emission problems inherent in transmission of electrical signals along interconnect lines (such as lines which connect transistors in integrated circuits). The apparatus includes one or more pairs of generally parallel interconnect lines. Each line in each pair comprises line sections, and an inverter is connected between each pair of adjacent sections of each line. The inverters are arranged in staggered fashion, in the sense that the inverters connected along each line of a line pair are offset longitudinally from the inverters connected along the other line of the pair. Both bidirectional and unidirectional buses (groups of generally parallel interconnect line pairs) can be implemented in accordance with the invention. The invention can serve as the basis for increasing the speed of computers and other electrical devices, and permits tight packing of transistors and interconnect lines with minimal crosstalk between the lines.

According to this invention a plurality of kinds of circuit blocks is formed as a circuit block area on a chip substrate to have a desired logic function. An array of signal output wires and array of signal input wires are formed adjacent the circuit block area such that these arrays intersect each other. First switching elements are each formed at a corresponding intersection of the signal output wire and signal input wire. An LSI device having a desired logic function can be implemented by electrically and fixedly writing an ON or OFF state of the first switching element. A first control wire and second control wire are provided adjacent to the circuit block area with the wire arranged parallel to the signal output wire and the wire arranged parallel to the signal input wire. Second switching elements are arranged at intersections of the first control wire and the signal input wires and at intersections of the second control wire and signal output wires. To a given circuit block, the output signals of the other circuit blocks can be supplied in a time-division fashion by controlling the second switching element, in real time, by virtue of a control circuit.

The relative sense of parallel propagating signals is inverted so reduce maximum transit time and transit-time variance. An integrated circuit comprises adjacent parallel signal paths, each extending from a respective driver to a respective load. Each signal path includes sense-inverting buffers and sense-preserving buffers arranged so that each sense-inverting buffer on one signal line is immediately adjacent to a sense-preserving buffer of the neighboring signal path. Signals co-propagating along the two signal paths have their relative senses inverted at each inter-path pair of adjacent buffers. As a result the crosstalk-induced tendencies of same-direction transitions to accelerate transition and opposing-direction transitions to retard transitions compensate for each other. In this way, the arrangement of sense-inverting and sense-preserving buffers reduces the maximum propagation delay across the signal paths and reduces the variance in propagation delays. Accordingly, the integrated circuit can be designed for faster transmission speeds and more precise timing--and thus better performance. The invention provides that the signal paths can be on the same or different metal levels, and can be implemented with or without sense-preserving buffers.

First and second wires are disposed adjacent to each other. Even pairs of buffers and inverters are disposed on the wires. A buffer and an inverter in each of the pairs are disposed on the first or second wires respectively. The first and second wires are respectively divided to even wire sections by the even pairs and a device or terminal connected to the output side of the pairs. Lengths of the wire sections are equal to each other between adjacent wire sections of the first and second wires. Gaps between the first and second wires are equal to each other between each two wire sections from the input side of the first and second wires.

A semiconductor memory device includes a plurality of input/output terminals (I/O1 to I/O4), a plurality of memory cell groups (1 to 4) and a plurality of sense amplifiers (31 to 34). A plurality of decision circuits (81 to 84) and a plurality of selection circuits (91 to 94) are provided in association with the input/output terminals (I/O1 to I/O4). A high voltage is applied to the input/output terminals that are not in use. This fixedly sets the corresponding sense amplifier groups to the non-activated state by means of the corresponding decision circuit and the selection circuit.