In a system for generating tests for digital circuits, a fault simulator (16) simulates a fault-free version of the circuit and all expected faulty versions of it concurrently, basing its operation on information contained in a data base (12) that contains information about the structure and possible defects of the circuits to be tested. A waveform system (14) carries high-level information regarding the general structure of the test waveform that ultimately is to be derived, such as clock signals, timing constraints, and other restrictions that the designer of the circuit under test has placed on the signals to be applied to it. At each point in this outline waveform at which the system needs to insert input signals, a test generator (18) is called by the waveform system (14) to derive a test vector based on information concerning the layout of the circuit, its possible defects, and its current state, the current state having been communicated to the data base (12) by the fault simulator (16), which determines the states that result from application of a waveform received from the waveform system (14). Even for non-scan-type circuits under test, the test generator derives only one test vector at a time, without searching through sequences of test vectors to find which sequences of test vectors might cause propagation of faults to the output ports of the circuit under test. It nonetheless efficiently derives test waveforms because it chooses among the fault effects of all faulty versions of the circuit concurrently for those effects that are likely candidates for propagation.

An integrated circuit having an array of logic gates adapted to provide predetermined logic functions on a plurality of input logic signals fed to the gate array and produce such predetermined logic functions as output signals at a plurality of array output terminals. A plurality of output buffer circuits are coupled between the outputs of an interconnected gate and the array output terminals. A circuit is provided for electrically decoupling each one of the plurality of logic output buffer circuits from the plurality of array output terminals in response to a common control signal. In a preferred embodiment, the control signal is fed to a single one of the plurality of array output terminals. With such arrangement, in response to the control signal, all logic outputs of the gate array are electrically isolated from other components wired to the gate array thereby allowing diagnostic testing of these other components in spite of the fact that they are wired to the gate array. It also allows parametric testing of three-state condition of the buffers required to be three-state buffers by the customer for normal device operation.

A programmable logic array, constructed in emitter coupled logic technology, may be tested in its non-programmed condition. Diodes are located between all product terminal lines and first test terminals on the semiconductor chip as they are disposed between all sum term lines and a second test terminal. Furthermore, each input line of the sum matrix is respectively connected by way of a diode to the inverting output of a respective different input amplifier. When the sum matrix exhibits more input lines than there are input amplifiers, the connection is repeated cyclically. In this case, the sum matrix is divided into sub-matrices whose mutually corresponding sum term lines are linked by way of logic elements.