A parity regeneration and self-check technique is used for detecting and locating errors in data communicated to, through, and from a digital subsystem. The invention utilizes a parity check associated with a data input of the subsystem, regenerating parity for data communicated from an output of the subsystem, checking the regenerated parity and comparing that check with other checks.

A mechanism for handling processing errors in a computer system. The mechanism includes a first means for processing a stream of instructions, second means for detecting an error caused by a timing dependant defect and occurring during processing of the instruction by the first means and third means for varying the instruction processing cycle time of the first means in response to the detection of the error by the second means, and for causing the second means to retry at least a portion of the instruction subsequent to the varying. In a preferred embodiment, the mechanism uses the variable frequency oscillator, controlled by recovery code, to increase the system clock cycle time by a specified time (Textend) following what has been determined to be a critical fail and after normal retry has been unsuccessful. The increased cycle time extends the net slack and, thereby, provides tolerance to certain AC (path delay) defects which have developed in any cycle time dependant latch to latch segment. The time (T) is chosen based on maximum cycle time restrictions resulting, for example, from the pipelining of data in system cables.

This is a multiplexing control unit comparing a plurality of subsystems completely separate and independent. Each subsystem is constituted as follows, and one objective device is controlled at the final stage output of the multiplexing control unit. A quantity or state of a plant is detected by a detector. A signal from the detector is output through a controller at each subsystem, and a normalcy decision signal for an output signal from the controller is output. A synthetic decision section selects one controller functioning most normally according to the normalcy decision signal of the output signal from the controller and outputs a control signal corresponding to the selected controller. An output signal switching section selects an output for the controller functioning most normally according to the control signal from the synthetic decision division to output to a device to be controlled.

A system for real-time digital signal processing employs a single-chip microcomputer device having separate on-chip program and data. An external program address bus allows off-chip program fetch in an expansion mode, with the opcode returned by an external data bus. A bus interchange module allows transfer between the separate internal program and data busses in special circumstances; for example, the internal program ROM may be read out on the data bus, one opcode at a time for test purposes, without executing the opcodes.

A system for securing a bus for a multi-processor system includes a plurality of processors connected in a closed loop so that each processor has a bus arbitration input signal output from the preceding processor and a bus arbitration output signal output to the following processor. The processor is judged to have the right to secure the bus when an exclusive logical sum of the bus arbitration input and output signals is a logical "1" and to have no right to secure the bus when the exclusive logical sum is a logical "0". The processor, when it is judged to have the right to secure the bus, reverses its bus arbitration output signal so as to abandon its own right to secure the bus and transfer the right to secure the bus to the following processor.