or
Bookmark and Share
Inter-subsystem communication system
   
Document Number
US Patent 4414620
Issued Date
November 8, 1983
Link
Map
Abstract
A communication system operation between computer systems which realizes highly efficient data transfer in a data processing system has sender and receiver subsystems operating under the control of an independent or common operating system. The communication system also includes: a plurality of sending buffers, a sending buffer address table having a plurality of entries and a buffer control block in the sender subsystem and a plurality of receiving buffers, a receiving buffer address table having a plurality of entries and a buffer control block in the receiver subsystem, and the communication path for transferring the data stored in the sending buffer to the receiving buffer.
Drawing
Inter-subsystem communication system - US Patent 4414620 Drawing
Drawing from US Patent 4414620
Tags:
Description:
Amusing 0%
Clever 0%
Complex 0%
Efficient 0%
Historic 0%
Important 0%
Innovative 0%
Interesting 0%
Practical 0%
Simple 0%
Number of Claims:
13
Comments:
no comments yet
Owner
Fujitsu Limited (Kanagawa,JP)
Published
November 8, 1983
Application Number
06/204,931
Filed
November 7, 1980
US Classification
709/217   709/234
Int'l Classification
G06F   15/16   (20060101)   G06F   13/12   (20060101)   G06F   15/17   (20060101)  
Attorney/Law Firm
Priority Data
Nov 12, 1979 [JP] 54-146164
USPTO Field of Search
364/2MSFile   364/9MSFile   370/60   370/61  
Related Patents
5195181 - Message processing system having separate message receiving and transmitting processors with message processing being distributed between the separate processors - Owned by Digital Equipment Corporation (Maynard, MA)

A scheme for efficient implementation of workload partitioning between separate receive and transmit processors is provided so that a message can be effectively moved through a multiprocessor router. Generally, each receiving processor collects, into a digest, information relating to network protocol processing of a particular message, obtained via sequential byte processing of the message at the time of reception of the message. The information placed into the digest is information that is necessary for the completion of the processing tasks to be performed by the processor of the transmitting line card. The digest is passed to the transmit processor through a buffer exchange between the receive and transmit processors. The transmit processor reads the digest before processing of the related message for transmission and uses the information in the network protocol processing of the message. Thus, the transmit processor does not have to "look ahead" to bytes of the message needed to complete certain processing functions already completed by the receive processor and does require extra buffering and/or memory bandwidth to make the modifications to the message.

5315707 - Multiprocessor buffer system - Owned by Digital Equipment Corporation (Maynard, MA)

The present invention is directed to a buffer swapping scheme to communicate a message from a first device to a second device wherein a pointer to a free buffer is returned to the first device by the second device as a condition for the first device to pass a pointer to a buffer containing a message intended for the second device.

5537639 - Method of communicating between CPUs within a copying machine with transmitting and receiving buffers divided into control flag area and data area - Owned by Mita Industrial Co., Ltd. (Osaka,JP)

A region of a communication buffer is divided into a control flag area where a communication mode flag and the like are set and a data area where communication data are set. In communication, a communication mode flag is set in the control flag area while communication data used in the specified communication mode are set in the data area. Thus, the data area can be shared among a plurality of communication modes. As a result, a capacity of the communication buffer can be reduced and the required communication period can be shortened.

5170473 - Communication command control system between CPUs - Owned by Fujitsu Limited (JP)

A communication command control system among a plurality of CPUs includes a control apparatus for transmitting an acknowledge signal to a request signal and thereafter for transmitting receiving command data and status data. The control apparatus comprises a local system priority determining circuit for determining a priority of signal processor commands from a plurality of CPUs and a local/remote system priority determining circuit for determining the priority between a local SIGP command controller and a remote SIGP controller. The data transfer period of the response request is detected when a response request is transmitted from another CPU of SIGP command control apparatus to the local and local/remote priority determining circuits, by counting the transfer period of command data after the response request is received and the acknowledge signal is transmitted and by counting the transfer period of the status data received from the other CPU. The system judges the destination of a CPU-ID representing the destination of said acknowledge signal, command data and status data.

4729095 - Broadcast instruction for use in a high performance computer system - Owned by Ncube Corporation (Beaverton, OR)

A broadcast pointer instruction has a first source operand (address pointer value) which is the starting address in a memory of message data to be broadcast to a number of processors through output ports. The broadcast pointer instruction has a first destination operand (first multibit mask), there being one bit position in the first mask for each one of the plurality of output ports. The address pointer value is loaded into each of the output ports whose numbers correspond to bit positions in the first mask that are set to be one, such that each output port that is designated in the first mask receives the starting address of the message data in the memory. A broadcast count instruction has a second source operand (a byte count value) equal to the number of bytes in the message data. The broadcast count instruction has a second destination operand (a second multibit mask), there being one bit position in the second mask for each one of the plurality of output ports. The byte count value is sent to each of the output ports whose numbers correspond to bit positions in the second mask register that are set to be one, such that each output port that is designated in the second mask receives the byte count value corresponding to the number of bytes in the message data that are to be transferred from the memory. Once the byte count is initialized, data are transferred from the starting address in memory over each output port designated in the masks, until the byte count is decremented to zero.

Claims
Description
About| FAQs| Terms & Disclaimer| Link to Us| Contact Us