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BACKGROUND OF THE INVENTION
This invention relates to data processing and, more particularly, to a data
processing system of the general type comprising first selection means for
selecting a plurality of characters of a first set, second selection means
for selecting a plurality of characters of a second set, display means for
displaying the selected characters of the first and second sets, and
control means responsive to the first and second selection means for
controlling said display means to display the selected characters of said
first set in a first display area and the selected characters of said
second set in a second display area.
An example of the above-type of data processing system used to process
Japanese language text is described in U.S. Pat. No. 4,193,119 filed on
Mar. 25, 1977 in the names of Shingo Arase and Roy J. Lahr for Apparatus
for Assisting in the Transposition of Foreign Language Test and assigned
to the assignee of the present invention. As described in that system, a
display is divided into two discrete display areas. A first display area
is used to display a portion of the Japanese text being created and which
may be composed of Hiragana, Katakana, Romaji and Kanji characters. The
second display area is used to display Kanji characters having a sound
similarity to a phonetic Japanese character or characters (e.g. Hiragana
or Katakana) just selected and made to appear in the first text display
area. A desired one or more Kanji characters may then be selected for
substitution into the text display area in place of the similarly sounding
Japanese phonetic character or characters that last appeared in the text.
It would be desirable to provide a data processing system of the general
type described in U.S. Pat. No. 4,193,119, where the concept of providing
multiple display areas could be expanded to display in a first display
area the complete page of text being created to thereby enable page
formatting and the like, and in addition to display in a second display
area a magnified portion of the page of text being created to thereby
facilitate editing and verification of the text. It would also be
desirable to provide a third display area for Kanji selection, as is done
in the second display area of the system of U.S. application Ser. No.
781,266. It would further be desirable if the second display area for
magnified viewing could be made adjustable in terms of its dimensions.
SUMMARY OF THE INVENTION
In accordance with one aspect of the invention, a data processing system is
provided comprising first selection means for selecting a plurality of
characters of a first set, said characters of said first set each being
defined by a bit map of first predetermined dimensions; second selection
means for selecting a plurality of characters of a second set, said
characters of said second set each being defined by a bit map of second
predetermined dimensions greater than said first predetermined dimensions;
display means for displaying the selected characters of said first and
second sets; and control means responsive to said first and second
selection means for controlling said display means to display the selected
characters of said first set in a first display area and the selected
characters of said second set in a second display area, said first display
area representing a page of text of characters of said first set, and said
second display area representing a magnified portion of said page of text
comprised of characters of said second set.
In accordance with the preferred embodiment, the first set of characters
include Hiragana, Katakana and Romaji characters, as well as a single
"dummy" character representative of all Kanji characters. All of these
characters of the first set are of first predetermined dimensions, e.g., a
bit map 7 bits wide by 7 bits high. These characters appear in a first
display area which is preferably a full page display to thereby enable
page formatting and the like. The Kanji characters normally cannot be
legibly reproduced in the full page display area, due to the size of the
bit map, the normal resolution capabilities of contemporary display
devices and the complexity of these characters. Consequently, a single
"dummy" character bit map is used to represent all Kanji characters of the
first set.
The second set of characters preferably include Hiragana, Katakana, Romaji
and Kanji characters.. In the preferred embodiment, the bit map dimensions
for each character of the second set, including all the Kanji characters,
are 18 bits wide by 20 bits high. The Kanji character subset is thus
capable of being legibly reproduced in the second display area. The
purpose of the second display area is to display a magnified portion of
the text being created and which is displayed in the first display area.
In accordance with a further aspect of the invention, the control means
includes means for selectively adjusting the dimensions of the second
display area. In this manner, a "window" defining the second display area
may be expanded to include as much of the text being created as is
necessary and required for easy text editing, creation and viewing. In
accordance with this aspect, it is posssible, if desired, to enlarge the
second display area to encompass the entire display so that only a
magnified portion of the full page of text being created is displayed.
Alternately, a second display area need not be used at all, the viewer
relying solely upon the text as depicted in the full page area. When both
display areas are used, it is possible to enlarge the window defining the
second display area to overlap that portion of the first display area not
presently containing text.
In accordance with a still further aspect of the invention, the control
means includes means for controlling the display means to display
preselected Kanji characters in a third display area, so as to enable easy
Kanji selection for substitution in the text in place of similarly
sounding Hiragana and Katakana phonetics, such as is accomplished in the
system described in U.S. Pat. No. 4,193,119.
BRIEF DESCRIPTION OF THE DRAWINGS
These and other aspects and advantages of the present invention will be
described below with reference to the accompanying drawings, wherein:
FIG. 1 is a perspective view of a data processing system of the present
invention;
FIG. 2 is a block diagram representation of the data processing system of
FIG. 1;
FIG. 3 is a representation of various storage areas in the main memory
depicted in FIG. 2;
FIG. 4 is a representation of various storage areas on the surfaces of a
magnetic recording disk included in the disk drive depicted in FIG. 2;
FIG. 5 is a top plan view of the array of keys included in the keyboard
depicted in FIG. 2;
FIG. 6 shows an exemplary image display on the display device depicted in
FIG. 2;
FIG. 7 shows a hypothetical display bit map generation control list stored
in the main memory of FIGS. 2 and 6, wherein the characters appear in an
ordered visual presentation sequence;
FIG. 8 shows the display bit map generation control list of FIG. 7, wherein
the characters are sorted into an ordered storage sequence;
FIGS. 9-11 depict the sequence of operations during which large character
strikes for display are loaded from the disk into data buffers defined in
the main memory of FIGS. 2 and 3, and then from the data buffers into the
bit map data portion of the main memory;
FIG. 12 is a block diagram representation of the control section of the CPU
shown in FIG. 2;
FIG. 13 is a block diagram representation of the data section of the CPU
shown in FIG. 2;
FIG. 14 is a block diagram representation of the display controller shown
in FIG. 2; and
FIG. 15 is a block diagram representation of the disk drive controller
shown in FIG. 2.
DESCRIPTION OF THE PREFERRED EMBODIMENT
At the outset of this description, it must be stated that the term
"character" as used herein is meant to imply not only recognizable
alphanumerics and language character forms, but also any graphical or
symbolic representation of any size, shape or geometric orientation.
Referring now to FIGS. 1 and 2, a data processing system of the present
invention is shown. The system includes a central processing unit (CPU) 10
that is comprised of a data section 12 and a control section 14. The
system also comprises a main memory 16 and a plurality of peripheral
devices, some of which having associated controllers. More specifically,
the system comprises a keyboard 18, a disk drive 20 with associated disk
drive controller 22, a display device 24 with associated display
controller 26, a cursor unit 28 with associated cursor unit controller 29,
a raster output scanned (ROS) printer 30 with associated ROS printer
controller 32, and a communications network 34 with associated network
controller 36. The keyboard 18 is unencoded and does not require a
separate controller.
Information is transferred to and from the data section 12 of the CPU 10 by
means of a main data transfer bus 38. The preferred processor 10 is
designed to handle 16-bits of parallel data, and so the bus 38 is
comprised of 16 parallel lines. The data bus 38 is connected not only to
the CPU data section 12, but also to the main memory 16 through a driver
and parity circuit 40 and a 32-bit memory data bus 42. Additionally, the
data bus 38 is connected to the disk drive controller 22, the display
controller 26, the cursor unit controller 29, the ROS printer controller
32 and the network controller 36, as well as to the keyboard 18.
Information is thus applied directly onto the data bus 38 from the
keyboard. On the other hand, the disk drive 20, display device 24, cursor
unit 28, ROS printer 30 and communications network 34 are each
input/output peripheral devices and information is transferred to and from
such devices through and by means of their respective controllers 22, 26,
29, 32 and 38. Thus, a suitable bus 44 is connected between the disk drive
20 and its controller 44, a bus 46 is connected between the display device
24 and its controller 26, a bus 17 is connected between the cursor unit 28
and its controller 29, a bus 48 is connected between the ROS printer 30
and its controller 32, and a bus 50 is connected between the
communications network 34 and its controller 36. The nature and
constitution of many of the signals transferred along the busses 44, 46,
47, 48 and 50 will be described below.
The disk drive controller 22, display controller 26 and network controller
36 are each capable of generating one or more task request signals in the
form of "wake-up" commands whenever it requires one or more services to be
performed by the CPU 10. The cursor unit controller 29 and ROS printer
controller 32 do not employ the use of task requests. The disk controller
22 is capable of generating two task request signals i.e. KSEC (Disk
Sector Task) and KWD (Disk Word Task). These signals are applied along
respective task request lines 52 to the CPU control section 14. The
display controller 26 is capable of generating three task request signals
associated with the display of data, i.e., DWT (Display Word Task), DHT
(Display Horizontal Task) and DVT (Display Vertical Task) that are applied
along respective task request lines 52 to the CPU control section 14.
Additionally, the display controller generates a CURT (Cursor Task) task
request signal periodically to enable the CPU 10 to execute a program
routine associated with the handling of cursor data. The network
controller 36 is capable of generating a single task request signal, i.e.,
NET (Network Task) that is applied along a respective line 52 to the CPU
control section 14.
Other task request signals are generated internally of the CPU 10 and
include MPT (Main Program Task), MRT (Memory Refresh Task) and PART
(Parity Task). The MPT task request signal is associated with the main
microprogram routine stored in the CPU control section 14 and is always
true, i.e., the main microprogram routine is always requesting service.
The MRT task request signal goes true every 38.08 is in order to refresh
information stored in the main memory 16. Lastly, the PART task request
signal goes true whenever a parity error is detected by the parity circuit
40.
In order for each of the controllers 22, 26 and 36 to be informed when the
CPU 10 is executing instructions relating to the requested service, the
control section 14 includes means to be described below for applying
"task-active" status signal back to the controller. These task active
signals are applied on lines 54 from the control section 14 to the
controllers 22, 26 and 36, as shown in FIG. 2. There are two task-active
lines 54 connected to the disk controller 22 (associated with the KSEC and
KWD tasks), four task active lines connected to the display controller 26
(associated with the DWT, DHT, DVT and CURT tasks) and one task-active
line 54 connected to the network controller 36 (associated with the NET
task).
Referring now in more detail to the CPU 10, and in particular to the
control section 14 thereof, it must be stated generally that the control
section 14 applies instructions to the data section 12 for execution
thereby. Additionally, instructions in the form of control signals are
applied along respective control lines 56 to the various I/O controls 22,
26, 29, 32 and 36 for execution thereby. The instructions are forwarded in
accordance with a particular sequence or routine to be carried out and
identified with a particular task to be serviced. The control section
includes means to be described below for determining which of a plurality
of wake-up task request signals applied to the control section 14 has the
highest current priority value. More specifically, each of the plurality
of tasks to be serviced is preassigned a unique priority value. Thus,
performing a requested service for the display controller 26 may be of
higher priority than performing a requested service for the network
controller 36. The control section 14 forwards instructions associated
with the highest current task to serviced to the data section 12 and
respective I/O controller for execution.
As indicated above, there are no task request signals supplied from the
cursor unit controller 29 and the ROS printer controller 32. Rather a
program routine associated with the processing of cursor information is
processed in response to the CURT task request signal initiated by the
display controller 26. The printing task is initiated by the operator
depressing a command key on the keyboard 18. This will cause a number of
selectable commands to be displayed on the display device 24 in a key top
area 96 (FIG. 6). One of the commands is a print command which can then be
selected by hitting a key on the keyboard 18 corresponding to the location
of the print command in the key top area. This entire concept will be
described in more detail below in connection with the description of FIG.
6. At this time, however, it should be noted that the print command signal
generated by the keyboard 18 is interpreted by the CPU 10 as a "Print Task
Request" which is then serviced in the manner described above.
Referring now in more detail to FIG. 12, the control section 14 of the CPU
10 includes a priority encoder 158 which has task request inputs connected
to the various task request lines 52 from the I/O controllers 22, 26 and
36, as well as to various output lines 162 from the decoders 160 for
receipt of the internally generated task request signals alluded to above,
e.g., MRT. The task request signal MPT, which requests servicing the main
program, is manifest by the grounded line 164 and is always true (low).
Thus, the main program is always requesting service. The priorty encoder
158 includes circuitry (not shown) for generating a multi-bit control
signal on a respective plurality of lines 166 related to the highest
priority wakeup-task request signal currently applied as an input to the
encoder 158. The priority encoder 158 includes a further input for
receiving a RESET signal on a line 168 from an initialize circuit 170 to
be described in more detail below.
Now then, the control signal developed on lines 166 is applied to
respective inputs of a current task register 172 which responds to such
control signal for generating a multibit address signal that is applied in
bit-parallel format on a respective plurality of lines from the register
172 to respective inputs of an address memory 176. The address memory 176
includes a plurality of storage locations, preferably defined by a
respective plurality of multi-bit registers (not shown). There are
preferably a number of registers included in the address memory 176 equal
to and respectively associated with the plurality of tasks capable of
being performed by the CPU 10, as alluded to above. Each register in the
address memory 176 is addressed by a unique multi-bit code defined by the
address signal applied thereto from the current-task register 172 on lines
174.
In accordance with the preferred embodiment, each of the registers in
address memory 176 is capable of storing the next address of an executable
microinstruction stored in a microinstruction memory 78. In this respect,
each of the plurality of address memory registers may be thought of as a
program counter for its respective task to be serviced relative to the
corresponding microinstruction routine stored in the instruction memory
178.
Each instruction stored in the memory 178 is accessed in response to a
corresponding address signal applied on address lines 180 from the address
memory 178. Each instruction includes an instruction field preferably
comprised of twenty-two bits, and a next-address field preferably
comprised of ten bits. The specific constitution of the 22-bit instruction
field, if desired, may be obtained through a review of Appendix A to and
forming part of this specification. The instruction field is loaded into
an instruction register 182 on lines 184 and is then applied through
appropriate decoders 160 (also described in more detail in Appendix A) to
the data section 12 of the CPU 10. Certain of these decoded instructions
are also forwarded to the I/O controllers 22, 26 and 36. The next-address
field is fed back on lines 186 to the currently addressed register in the
address memory 176. In this manner, each of the plurality of registers in
the memory 176 will always contain the address of the next
microinstruction stored in the instruction memory 178 to be executed in
accordance with the particular task to be serviced.
A portion of the twenty-two bit instruction field of each microinstruction
may be dedicated to various special functions, some of which are applied
on control lines 188 to respective ones of the I/O controllers 22, 26 and
36 for controlling same, and some of which are applied on control lines
190 to address modifier circuits 192 for branching. In accordance with the
preferred embodiment, there is a four-bit special function "sub-field" in
the instruction field of each microinstruction, wherein two of the sixteen
four-bit codes capable of being defined are respectively representative of
"TASK" and "BLOCK" functions. A TASK signal component of an accessed
instruction, upon being decoded by an appropriate one of the decoders 160,
is applied on a line 194 to the current task register register 172 for
enabling the register to load an address signal, representing the current
highest priority task requesting service. This address signal is then
applied to the address memory 176. A decoded BLOCK signal is applied on
another line 194 to the current task register 172 for disabling same.
The multi-bit address signal developed at the output of the current task
register 172, in addition to being applied to the address memory 176 on
lines 174, is also applied on lines 196 to a task-active decoder 198. The
decoder 198 responds to the address signal output of the register 172 and
generates one of the plurality of TASK-ACTIVE signals alluded to earlier
on its respective line 54, dependent upon the current highest priority
task to be serviced. The decoder 198 includes a delay circuit for delaying
the application of a TASK-ACTIVE signal to the respective I/O controller
by one clock cycle of the processor. In this manner, the appropriate
TASK-ACTIVE signal will be generated at a time corresponding to the
execution of instructions related to the task being serviced.
The control section 14 as shown in FIG. 12 also includes a clock generator
200 for generating appropriate CLOCK signals for application to the
current-task register 172 on a line 202, the task-active decoder 198 on a
line 204, the address memory 176 on a line 206, and the initialization
circuit 170 on a line 208.
Still referring to FIG. 12, the initialization circuit 170 is responsive to
a START signal generated when the system is turned on by the operator.
Upon receipt of the START signal, conventional circuitry in the circuit
170 causes a RESET signal to be generated which is applied to the priority
encoder 158 on line 168, to the current task register 172 on a line 210,
to the task-active decoder 198 on a line 212, to the instruction memory
178 on a line 214, to the instruction register 182 and decoders 160 on a
line 216, and to the address modifier 192 on a line 218. Upon receipt of a
RESET signal, these various components of the control section 14 are
reset.
The initialization circuit 170, in response to a START signal, also
generates a multi-bit initialization address signal on a respective
plurality of lines 220. In a preferred embodiment of the invention, their
are sixteen possible tasks and associated registers in address memory 76.
Thus, the initialization address signal is a four-bit signal that is
initially zero, i.e., 0000, and is incremented by one at the rate of the
CLOCK signal pulses applied on line 208. The RESET signal is maintained
for sixteen cycles, i.e., sixteen CLOCK signal pulses, at which time the
initialization address on lines 220 will increment from zero (0000) to
fifteen (1111). The address signal output of the current task register 172
during initialization is identical to the initialization address signal.
During initialization, the address signal output of the current task
register 172 is applied through an AND-gate 222, which is enabled by a
RESET signal from the initialization circuit 170, to the address memory
176. In this manner, the address signal (0000) will be loaded into
register number zero in the address memory 176, the address signal one
(0001) into register number one, and so on. This process initializes the
address memory by setting the various registers therein at their
respective starting values.
Further details of the preferred CPU control section 14, if desired, may be
obtained through a review of of the manual entitled "ALTO: A Personal
Computer System Hardware Manual", January, 1979 available from Xerox
Corporation, 3333 Coyote Hill Road, Palo Alto, CA 94304 as well as U.S.
Pat. No. 4,103,330.
Referring now to FIG. 13, the data section 12 of the CPU 10 preferably
includes a number of 16-bit registers, such as a pair of 32 word register
files (R register file 224 and S register file 226) and a number of single
word registers (T register 228, L register 230, M register 232, memory
address register (MAR) 234 and instruction register (IR) 236). The data
section 12 also includes an arithmetic logic unit (ALU) 238, a pair of
multiplexers 240 and 242, a PROM 244, a shifter 246, a constant memory 248
and a main memory decode and control circuit 250.
As shown in FIG. 13, the multiplexer 242 has a first data input connected
to the data bus 38 for receiving data therefrom and a second data input
connected to the output of the ALU 238. A control input of the multiplexer
242 is connected to an output of the PROM 244 for controlling the
multiplexer in terms of which data input is to be applied at its output.
The output of the multiplexer 242 is connected to the T register 228. Load
control of the T register is accomplished by a control signal from the
control section 14, while the output of the T register 228 is connected to
the ALU 238. The ALU 238 is restricted by an output of the PROM 244 into
16 possible arithmetic and logic functions. The PROM 244 is controlled by
4 control lines from the control section 14 of the CPU 10. The output of
the ALU 238 is connected to inputs of the L register 230, M register 232
and MAR 234, as well as to the multiplexer 242, as indicated above.
A load control output of the L register 230 is connected to a second input
of the M register 232 for controlling the loading of data therein, whereas
a second inverted output of the L register 230 is connected to an inverted
input of the shifter 246, which is capable of left and right shifts by one
place and cycles of eight. Load control of the L register 230 is effected
by a load control signal applied from the control section 14. The output
of the shifter 246 is connected to an inverted data input of the R
register file 224, whereas the output of the M register 232 is connected
to an inverted data input of the S register file 226. The outputs of both
register files 224 and 226 are connected to the data bus 38. The various
functions of the shifter 246 are controlled by control signals from the
control section 14. The register files 224 and 226 also receive control
signals from the output of the multiplexer 240 and are addressed by
address control signals from the control section 14. The multiplexer 240
itself receives various input control signals from the control section 14.
The MAR 234 has its output connected to the memory address bus 80 for
applying a 16-bit address signal to the main memory 16. Additionally, this
16-bit address is applied to the decode and control circuit 250 which
applies control signals to the main memory 16 on lines 82. These control
signals are associated with the manner in which the 16-bit values stored
in main memory are transferred over the 32-bit memory data bus 42 to the
drivers and parity circuit 40.
The instruction register 236 is used by an emulator microcode routline to
hold the current emulated microinstruction. The input of IR 236 is thus
connected to the data bus 38, as is a 16-bit output. Additionally, various
output bits (1-4) of the 16-bit output are connected on output lines to
the multiplexer 240. Lastly, the constant memory 248 is preferably a 256
word by 16-bit PROM that holds arbitrary constants. The constant memory
output is connected to the data bus 38 and is addressed by control signals
from the control section 14, as shown.
Further details of the preferred data section 12, if desired, may be
obtained through a review of of the manual entitled "ALTO: A Personal
Computer System Hardward Manual", January, 1979 available from Xerox
Corporation, 3333 Coyote Hill Road, Palo Alto, CA 94304, and details of an
earlier alternative embodiment may be obtained through a review of U.S.
Pat. Nos. 4,103,331 and 4,148,098.
Reference is now had to FIG. 3 where the main memory 16 will be described
in more detail. At the outset, it should be noted that memory 16 is
preferably an 850 .mu.s error corrected semiconductor memory capable of
storing 65,536 16-bit words. A first section 60 of the memory 16 is
capable of defining and storing a bit map representation of an image to be
displayed on the display device 24, or a "slice" or segment of an image or
page to be printed on the ROS printer 30. This slice may be either
lengthwise or widthwise in orientation, but is desirably widthwise. In
accordance with the preferred embodiment, the resolution capabilities of
the printer 30-are significantly greater than that of the display device
24. Accordingly, it is not possible to create an entire bit map for a page
to be printed in the bit map data section 60. Consequently, the bit map
for a page to be printed is created on a disk in the disk drive 20 and
then transferred in widthwise slices, each a predetermined number of bits
in length. The slices are transferred to the memory 16 and then to the ROS
printer controller 32 one slice at a time, as will be discussed in more
detail below.
A second section 62 of the main memory 16 is adapted to store "display
control blocks" and "disk command blocks", both referred to generically as
"DCB's". The purpose of DCB's will be described below in connection with a
description of the display controller 26 and the disk drive controller 22.
A third section 64 of the main memory 16 is adapted to store character font
data for a first set of characters, i.e., "small" characters for display.
These small display characters preferably comprise Romaji (English
alphanumerics), Katakana and Hiragana character sub-sets, wherein each
character is desirably defined by a 7.times.7 bit map matrix.
Additionally, due to this relative small scale and the degree of
complexity of the Kanji character sub-set, a single "dummy" Kanji
character comprised of a predetermined 7.times.7 bit map matrix pattern is
included in the small display character set (see character numbered 65 in
FIG. 6). Desirably, only small display characters are displayed in a first
page display area 66 on the display device which is used for page
formatting purposes and the like. This concept will be discussed in more
detail below relative to FIG. 6.
A fourth storage section 68 of the main memory 16 defines a pair of data
buffers 70 and 72 (FIGS. 9-11). The purpose of these data buffers is to
receive "strikes" of large display characters from the disk drive
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