In a data processing system having a host processor, a cache store for storing segments of data, a bulk memory and a storage control unit for controlling transfers between the processor, cache store and bulk memory, the storage control unit normally responds to a read or write command from the host processor to control the transfer of data. If a copy of the data transferred is not resident in the cache store then a copy is written therein by the storage control unit. If the length of a data transfer exceeds a first threshold length then the storage control unit does not write a copy of the data into the cache store. If the length of a data transfer exceeds a second threshold length, and the transfer begins on a segment boundary and comprises an integral number of segments, then the storage control unit does not write a copy of the data into the cache store. The writing into the cache store is transparent to the host processor. The use of a transfer threshold prevents data from being entered into the cache store when it is not likely to be used again soon. Two thresholds are provided because the data transferred in long transfers of an integral number of segments is even less likely to be used again soon than the data transferred in long transfers that do not begin on a segment boundary or comprise an integral number of segments.
A control system for a disk cache memory is disposed between a main memory unit and a disk unit for storing a record of data from the disk unit. The control system is designed such that when an input/output instruction is issued from a CPU while data loading is being performed from the disk unit to the cache memory, it interrupts the data loading once so that an input/output instruction from the CPU can be executed, thereby considerably reducing the time of wait for execution of the input/output instruction.
A cache bypass mechanism automatically avoids caching of data for instructions whose data references, for whatever reason, exhibit low cache hit ratio. The mechanism keeps a record of an instruction's behavior in the immediate past, and this record is used to decide whether its future references should be cached or not. If an instruction is experiencing bad cache hit ratio, it is marked as non-cacheable, and its data references are made to bypass the cache. This avoids the additional penalty of unnecessarily fetching the remaining words in the line, reduces the demand on the memory bandwidth, avoids flushing the cache of useful data and, in parallel processing environments, prevents line thrashing. The cache management scheme is automatic and requires no compiler or user intervention.
In a magnetic disk controller equipped with a cache memory for disks, the controller in accordance with the present invention includes high order paths for data transfer between a high order channel apparatus and the cache memory through a certain one of a plurality of channel adaptors, low order paths for data transfer between a low order device, e.g. a magnetic disk device, and the cache memory through a certain one of a plurality of device adaptors and a path for data transfer betweeen the low order device and the channel cevice without passing through the cache memory by selecting empty device adaptor and channel adaptor by the switching operation of a switch. When an interrupt is generated from the device, data transfer can be made easily even when the high order path and the low order path are busy, and path utilization efficiency can be improved.
A cache system which, when a cache is a bus master, puts a CPU in a standby state and makes effective a signal common to the CPU and cache and a signal decided only by the cache, or when the CPU is the bus master, makes effective the signal common to the CPU and cache and the signal decided only by the CPU, or when at a cache miss, the cache gives the CPU a control signal requesting reexecution of memory access and a control signal to allow the memory system to accept memory access to thereby operate the cache dependently on the CPU, so that even when either the CPU or the cache is the bus master, signal transmit-receive with respect to the memory system is adapted to be carried out substantially at the same timing. Furthermore, where a cache miss occurs when the CPU accesses to single data, and in order to cope with the case that a plurality of data from the memory system to the cache are transferred, the data of address next to the accessed address by the CPU is initially transferred from the memory system to the CPU, thereafter data is transferred to the CPU while changing the address in a so-called round robin method, and at last the object data for the CPU is controlled to be transferred in parallel to the CPU and cache, thereby minimizing the number of times for data transfer from the memory system to the cache.
A computer system includes a memory capable of storing a plurality of data words, and a central processing unit for outputting data words to be stored in the memory. A method and apparatus for facilitating transfer of the data words from the central processing unit to the memory involve accepting and temporarily storing in a storage portion each data word from the central processing unit and then subsequently storing in the memory each temporarily stored data word, the maximum number of data words which can be temporarily stored being selectively set to one of first and second values which are different.
