A memory system for simultaneously extracting a desired block of data in response to an address specifying only the center bit of the block. The input address is modified through an arithmetic circuit wherein the address representing the center bit is added to and subtracted from to produce a plurality of addresses which are used to address a plurality of separate memory blocks. The outputs from the memory blocks are passed through a selection alignment matrix circuit which selects from the outputs of the memory blocks only those bits in the desired block of data and aligns those bits in a predetermined array. Bits other than those in the desired block of data are discarded.
An image processing apparatus that processes image data consecutively in the column and row directions has an image memory, a reading unit, a temporary memory and an operative unit. The image memory stores image data consecutively in column and row directions on a pixel unit basis. The reading unit reads from the image memory a series of pixels within one column at one row and at least one pixel adjacent to the one row in the column direction. The temporary memory sequentially stores a number of groups of pixels read from the reading unit as is necessary for image processing. The operation unit reads the values of an objective pixel and pixels necessary for a neighborhood operation of the objective pixel from the temporary memory, and subjects the values to a neighborhood operation to determine the output value of the objective pixel.
In the image processor system of the invention, an image processor and a plurality of image memories are connected through a plurality of image buses. The image processor and image memories are also connected through a control bus, as is a CPU. The image processor has a start signal output gate circuit. When the gate circuit is initiated by the CPU, it simultaneously outputs start signals designating image data output to the image buses designated by the CPU. Each image memory has a start signal input gate circuit and an output gate circuit. The start input gate circuit receives the start signal from the image bus designated by the CPU through the control bus. The output gate circuit starts image data output to the designated image bus in response to the start signal received at the start signal input gate circuit and in synchronism with the bus cycle of the image bus.
A system for combining a plurality of video signals and various forms of still imagery such as text or graphics into a single high resolution display is disclosed. The inventive system utilizes a multiport memory and a key based memory access system to flexibly compose a multiplicity of video signals and still images into a full color high definition television display comprising a plurality of overlapping windows.
A graphic display PC/interface system is described which includes three memory units: a source memory which is addressed in planar byte increments and stores display data units on a bit per plane basis; a target memory for storing display data units in a manner suitable for operation of a display unit; and a window buffer for transferring display data unit from the source memory to the target memory. The system transfers a quantity of display data unit bytes from the source memory to the target memory by accessing pairs of planar bytes, which pair of planar bytes may have a display data unit byte bridging therebetween. The method comprises selecting a first pair of planar bytes from the source memory; aligning the display data unit byte which lies totally within the selected first pair of planar bytes; selecting a second pair of planar bytes from the source memory; aligning a display data unit byte which lies totally within the second selected pair of planar bytes; consolidating the display data unit byte which bridges between the first and second pairs of selected planar bytes; aligning the consolidated display data unit byte; and transferring aligned display data unit bytes to the window buffer.
A method of operating a digital computer includes the steps of addressing a memory, reading a row of data from the memory, providing the same computational instruction simultaneously to each processor element of a plurality of processor elements, where each of the processor elements is selectively coupled to a corresponding bit position of the memory row of data, performing the same computational operation on a selected plurality of data bits in parallel, and writing the result into the memory at the same row from which the data was read.
