A video display memory expansion system for expanding the graphics memory within the video display. The memory expansion system is suited for increasing the resolution of a graphics display from a low-resolution to a high-resolution display. A video display device is adapted to receive a relatively simple graphics memory expansion accessory to thereby easily and inexpensively provide the increased graphics memory capability.
A video display control system is capable of moving a part of a still image from a first display area to a second display area on a screen. The video display control system includes a memory composed of a plurality of memory locations for storing a plurality of display data representative of images of display elements on the screen. First and second registers retain first and second area data representative of the first and second display areas, and an address data generator generates from these area data first and second address data, the first address data indicating memory locations which store display data corresponding to the first display area, the second address data indicating second memory locations which store display data corresponding to the second display area. A reading circuit reads the display data in the first memory locations in accordance with the first address data, while a writing circuit writes the read display data into the second memory locations in accordance with the second address data. This video display control system further includes another reading circuit and an operation circuit. This reading circuit reads the display data in the second memory locations and feeds the read display data to the operation circuit which effects an operation such as a logical operation or a transparency processing on each pair of the display data read from the first and second memory locations.
A video display controller supplies a raster address signal to a video memory for sequentially reading out a series of video data codes, and comprises a first data register for memorizing a control data code indicative of a bit length to be circulated in a rewritable manner, a second register for memorizing a repetition rate code indicative of a repetition pattern of the raster address in a rewritable manner, a combination of a shift register and a selector supplied with the repetition rate code in synchronism with a frame clock signal and circulating the data bits of the repetition code indicated by the control data code in synchronism with a line clock signal and a raster counter responsive to an enable signal fed from the selector and latching the line clock signal for incrementing the raster address, wherein the raster address is incremented or maintained depending upon the data bit at a predetermined bit position serving as the enable signal, so that the series of video data codes are repeatedly read out from the video memory for enlarging visual images on a screen.
A device independent system and method of displaying text on a graphics display device. The system provides programmed routines in a storage device located on a controller card for the graphics device. These routines are loaded into memory by an operating system during initialization of the operating system. Once loaded, the routines become an extension of the operating system to provide the means for displaying information on the graphics device. Each type of graphics device contains a storage device that provides a set of access routines specifically programmed for the device. These routines have a standard interface across all devices, allowing displaying of textual information to be device independent. The storage device contains multiple sets of routines, one for each processor type capable of utilizing the graphics device, thus processor independence is achieved.
A direct memory access apparatus includes a CPU, and data of one byte or more to be transferred is stored in a working RAM of the CPU or an external storage unit. The external storage unit includes a memory cartridge or a CD-ROM, and stores parameter data including the number of data to be transferred, and a first address and second address for direct memory access. Prior to a start of the direct memory access, the parameter data is read and, when a horizontal blanking signal is generated from a counter included in a video processor, the data is read from the working RAM or the external storage unit in accordance with the first address value and the data is transferred to an internal memory of the video processor in accordance with the second address value.
A video field memory device for multi-broadcasting system employs upper and lower half memory cell arrays for storing a video signal according to the largest scanning bit and the largest scanning line of the multi-broadcasting system, and the upper and lower half memory cell arrays having the scanning bits of 1023.times.4 and the scanning lines of 313.times.4 corresponding to the largest one of various television broadcasting systems. Thus, the video field memory device for multi-broadcasting system for varying the scanning bits or the scanning lines can select a broadcasting system in a single chip by using a external TYPE signal, independent of the scanning bits or the scanning lines for each television broadcasting system.
