A dynamically programmable processing element (DPPE) is disclosed which element has the utility in a digital processing system which requires complicated arithmetic procedures to be implemented. The DPPE device is a special purpose computer which essentially has a program bus for transmitting and receiving program data from an external source. A data bus is also provided which bus can transmit or receive digital data. Coupled between the buses are input and output registers or buffers which are capable of storing transmitted or received data propagating on either of said buses. A program memory has an input coupled to said program bus and means coupling the output of the program memory to the program bus. A data memory has an addressable input means coupled to the program bus and an output coupled to the data bus. Based on the orientation of the buses and the memories, the program memory can receive program information or data from an external source and data from the data memory can be transferred to the external source. In this respect the DPPE can be reprogrammed in real time by the external source. The DPPE can also execute program instructions by fetching them from the external source as well as executing its own program instructions as stored in its program memory. The structure and format of the DPPE enables it to interface with an external source such as a microprocessor to assist and perform program instructions, as well as to perform arithmetic operations on data from the microprocessor and to communicate with the microprocessor after completion of the various routines.
There is disclosed a multiple processor system which employs dynamically programmable processing elements (DDPE) utilized as slave devices and under the control of a master processor. A plurality of DPPE's have input/output data lines connected to a digital signal processing (DSP) bus. Communication between the DPPE's is afforded via the (DSP) bus from a master processor which interfaces with the bus via a dual port memory designated as a global memory. Each DPPE is connected together via another bidirectional serial bus so that the individual DPPE's can communicate one with the other in regard to processing and exchanging of arithmetic data. The digital signal processing bus allows the master processor to interface with the DPPE devices for control of input/output and control functions. In this manner, the master processor interfaces directly with a codec and has outputs which allow the transmission of plaintext or ciphertext data which data is formed by arithmetic operations performed by the slave DPPE's. The master processor also accesses a host computer and user terminal via a deuce circuit which essentially is a dual enhanced communications element. The status of the DPPE's and priority between the DPPE's and the master processor is controlled by an arbiter circuit which essentially controls the access of the DPPE's to the dual port memory (global memory) via the digital signal processing bus. The system is employed to operate on complicated algorithms and is patricularly adapted for use as a voice processor or modem processor is regard to modern communications systems.
A circuit for converting a TV receiver to operate in accordance with the system associated with received signals, there being either F or F' scan lines in a field, with F<F', includes a counter driven by pulses each representative of one end of a raster scan line, and having M stages, with F and F'<M<2F and 2F'. There is also means to preload the counter selectively with a count of R or R', where (M-2R)=F and (M-2R')=F'. Wide window means detects when a field sync pulse is within a window including the (M-R)th and (M-R') stages, and, in response, the counter, initially, is preloaded with R'. Decision logic means then detects whether a field sync pulse occurs after the Kth stage, with K=M-[R+R']/2, when R' is continued to be preload; or occurs before the Kth stage, when R subsequently is preloaded; and the required TV receiver conversion is completed.
A monolithic digital signal processor includes a core processor for performing digital signal computations, an I/O processor for controlling external access to and from the digital signal processor through an external port, first and second memory banks for storing instructions and data for the digital signal computations, and first and second buses interconnecting the core processor, the I/O processor and the memory banks. The core processor and the I/O processor access the memory banks on the first bus without interference on different clock phases of a clock cycle. The internal memory and the I/O processor of the digital signal processor are assigned to a region of a global memory space, which facilitates multiprocessing configurations. In a multiprocessor system, each digital signal processor is assigned a processor ID. The digital signal processor includes a bus arbitration circuit for controlling access to an external bus through the external port. The digital signal processor may include one or more serial ports and one or more link ports for point-to-point communication with external devices. A DMA controller controls DMA transfers through the external port, the serial ports and the link ports.
Disclosed are a single-chip micro-computer optimized for an electronic memorandum book, an electronic dictionary or the like by suppressing the increase of the number of terminals, and an electronic apparatus having therein the single-chip micro-computer. The single-chip micro-computer has: a mode setting register for establishing a mode setting signal for either a first mode for outputting a memory address signal or a second mode for outputting an arithmetic operation output stored in an output register on the basis of a control signal from a micro instruction generation circuit; and a selection circuit for outputting either the memory address signal or the arithmetic operation output to address signal terminals on the basis of the mode setting signal.
The present invention provides methods and apparatus for upgrading firmware in an embedded system, without impacting the system. More specifically, the present invention enables an embedded system to be upgraded without any system downtime, by providing two application areas in non-volatile programmable read only memory. A processor can boot up and run from either application area. A fixed vector table is provided, which, in cooperation with a software vector table, enables the processor to maintain proper interrupt vector addresses while being able to run from either application area. Upgraded firmware can be loaded into one application area while the system is running from the other application area. Resetting the processor allows the system to run the upgraded version of firmware.
