This video graphics raster display system effectively facilitates panning over an image that is arbitrarily larger than the image memory from which the display is generated. To accomplish this, the image memory is addressable "toroidally", i.e., in modulo or wraparound fashion. Thus, if a memory address boundary is reached during a raster readout, the readout continues without interruption from the opposite boundary. The image memory is slightly larger than would be required to store only the image currently being displayed. The excess memory area includes a border area, surrounding the current readout area, which contains image data that forms a continuation of the image currently being read out and displayed. This allows immediate panning into the border area. Further, the excess memory area includes a "rewrite area" on the other side of the border zone from the current readout area into which new, image continuation data may be entered while panning takes place. Appropriate circuitry facilitates new data entry to the rewrite area and controls the panning rate to ensure that the displayed image will not reach the rewrite area until after the new data has been entered.
A system for generating a real time perspective view of the terrain lying along an aircraft's flight path accesses terrain data stored in a digital map generator and converts the data into a perspective representation of the terrain on the face of a suitable display such as a cockpit instrument panel CRT. The stored map data that is accessed provides, in real time, information pertaining to elevation features of the terrain over which the aircraft is flying, so that upon conversion to a perspective presentation to the pilot, there is provided a real time perspective image of the contours of the terrain as though the pilot were looking out a windscreen at the terrain in high visibility conditions. The invention also is capable of providing perspective scene rotation and translation (corresponding to roll and pitch of the aircraft).
An image processing system is disclosed which includes: a control computer which has a CPU and a main memory therein; and an image memory section which is connected to the CPU through an interface and which has an image memory for digitally storing image data, a memory controller and an image processor. A memory area as part of the main memory is independently allocated to store as a register area data transferred through a privately leased data bus which bypasses the interface between the control computer and the image memory section. When random access operation of the image data with respect to the image memory is performed, the data transfer between the CPU and the image memory section can be performed through the memory area (register area) and the special data bus without going through the interface.
In a graphics display system, a cursor is used to pan a viewport relative to a block of stored information only part of which is selectable to be viewed through the viewport. As long as a cursor remains within the viewport, it can be utilized in a conventional manner under the control of a mouse or the like to provide interaction with display information. When the cursor is moved outside the viewport of the display, the viewport is panned to include the cursor.
A LCD vertical scrolling mechanism automatically tracks addresses of information scrolled on a LCD. A counter is initialized to a value latched in a vector register when a frame signal is received. Subsequent BPCLK signals step the adder through a series of values. These values are relayed through two bus selectors to segment drivers for the LCD. One of the bus selectors is coupled to the counter in parallel with a subtracter. When a value from the counter exceeds a predetermined value equal to the MUX of the LCD, the subtracter takes the difference between the predetermined MUX value and the value received from the counter and directs the parallel bus selector to relay the difference to the RAM of a segment driver. An adder is coupled to the other bus selector and to the vector register. When the MCU needs to fetch information from the segment drivers, the MCU relays a LCD address where the information is displayed, to the adder. The adder adds the address (a value) to the value latched in the vector register. The MCU directs the second bus selector to select the value determined in the adder and relay this address to the segment driver.
By selecting the starting time of the display readout of a pel buffer raster generation, the pel data is mapped to a display screen with an arbitrary displacement with respect to the screen for relocation or scrolling of the pel image on the screen. To compensate for non-congruency between the pel data window and screen viewport definitions and to provide scrolling on a pel basis, the positioning of the window on the screen includes fine adjustment achieved by a determinable delay between the scanning of the buffer and the generation of the screen raster. The display circuits include means to extend the window background to fill in gaps between the edges of a window of pel data chosen to be displayed and a larger screen viewport in which it is to be displayed. System read/write access times to the buffer are interleaved with and synchronized to the data fetch times of the display.