There is described a unique apparatus for exchanging commands and data via a dedicated memory which has ports connected to the data and address busses of two different microprocessors. The system operates even though the microprocessors have different word lengths, e.g. a sixteen bit processor and an eight bit processor. The system permits interfacing between the microprocessors with different bit size words and allows each of the microprocessors to treat the exchange memory as part of its own memory space without locking one microprocessor off of a shared bus.
A dual processor system in which one processor is dedicated to input/output tasks while the other is dedicated to high level language tasks when operating as a 16-bit machine. The processors include a first microprocessor which is an 8-bit machine, and a second microprocessor which is a 16-bit machine. The first processor has a memory associated therewith which may, for example, be a 64K memory while the second processor has a larger capacity memory. The second processor does not access the memory of the first processor, however, the first processor can access a portion of the second processor's memory. Access to the second processor's memory is controlled by an arbitrator that is operated by system software to prevent access conflicts. For boot-up during power-up operation, a boot ROM is used, attached to the 8-bit processor having stored therein a boot strap program that is initially loaded into the 8-bit processor memory. If the operating system loaded from a diskette indicates 8-bit software, then the 16-bit processor is maintained reset or halted. On the other hand, if the operating system is a 16-bit system, then the boot program loads the 16-bit memory making the 16-bit processor the main processor. The 8-bit processor then functions as an I/O processor. This boot-up procedure allows the 8-bit processor to turn on first and makes the system initially appear as an 8-bit processor system. In this way the system is compatible with software written for an 8-bit machine even though the system is normally run and identified as a 16-bit machine.
A removable CPU module for use in a data processing system. The CPU module includes at least one CPU having a first data width, and a first data bus of the same data width coupled to the CPU. A connector is coupled to the first data bus for connecting to a circuit board having a second data bus. The second data bus has a second data width which is different from the first data width. The CPU module is configured such that it is compatible with the second data bus. In one embodiment, the removable CPU module includes a third data bus coupled to the first data bus and the connector, which is a duplicate of and connected in parallel with the first data bus. The third data bus facilitates compatibility between the CPU module and the second data bus.
A microcomputer generates signals representative of character data. The character data are stored in a second area of a first memory which also has a first area storing a program. When character display information is generated, the second area of the first memory is cyclically made access to read the character data therefrom. The character data read from the first memory are stored temporarily into a second memory. The character data stored in the second memory is transferred to a shift register in response to a character output command signal and then outputted in response to a shift clock pulse.
A multi-processor system that is useful for controlling processes of motor vehicles. The system having at least two processors that jointly access the same memory. The system memory is divided into at least two sectors. A first processor accesses one memory sector only in the read mode and a second processor accesses it only in the write mode. The second processor accesses the other memory sector only in the read mode and the first processor accesses it only in the write mode. The processors are synchronized in such a way that the processors access the memory in the same way at the same time.
In a multiprocessor system in which bidirectional data transfer is effected among a plurality of processors through at least one data buffer permitting the transfer data to be read therefrom and written thereinto, judgement is made as to whether the transfer data can be read from the data buffer and/or written thereinto on the basis of information about the read and/or write addresses of the data buffer, and the processing of each of processors is interrupted on the basis of the result of the judgement to cause the processor to read the transfer data from the data buffer and/or write it thereinto.
