If each data channel comprising a set of multiplexed data channels contains channel identity information, a single framing detector operating on one channel can provide a framing detection operation regardless of where the search is commenced thereby avoiding a search of all of the channels to obtain framing information. By having unique tag or identity bits incorporated in each of the multiplexed data channels, the timing problems for obtaining synchronized parallel output bits from each of the channels can be logically ascertained and the channels can be rerouted and individual channels of the rerouted channels can be time delayed to obtain the time synchronization.

A method and apparatus for synchronizing a digital data signal from a first location, such as a digital telephone station, and which is transmitted to a second location, such as the station interface of a telephone switching system common equipment input, with a digital data signal at the second location, is disclosed. The method includes transmitting a data signal to the second location from the first location, receiving the data signal at the second location and determining if the data signal is present at a selected time. Digital coded data is sent to the first location from the second location for selecting successive delay times at the first location. When the delayed data signal is present at the second location at the selected time, the optimum value of the delay time is determined at the second location, preferably by averaging the values of the delay times at which the data signal was first detected and last detected at the second location. Digital coded data corresponding to the optimum delay time is then sent to the first location to select the optimum delay time at the first location.

A N-stage synchronizer for synchronizing asynchronous signals in a destination system's time domain. The synchronizer has N-stages with each stage having a series connected logic gate and flip-flop, and each of the N-stages are connected in series. Each logic gate has the output of the previous stage input thereto along with an ABORT signal. The ABORT signal when asserted blocks the synchronization of the asynchronous signal. The synchronizer permits a reduction in the latency associated with the synchronization process while not affecting reliability.

A phase adjustment circuit uses a broad band circuit for processing a plurality of high speed highway data comprising m bit frames. The phase adjustment circuit provides a master frame pulse based on a frame pulse selected from respective frame pulses in the high speed highway and delayed in phase by the maximum amount and provides a master clock based on a high speed highway clock corresponding to the master frame pulse. The phase adjustment circuit receives a plurality of high speed highway data by using the master clock and the master frame pulse.

In a method of synchronizing synchronous digital bit streams each comprising bits each having the same duration, one of the bit streams is taken as a reference. This provides a basis for defining successive reference time intervals each equal to the bit duration. A plurality of timing windows are defined within each reference time interval. A second bit stream is subjected to a time-delay that can have a null or zero value. One of the windows is taken as a reference window on the basis of a required phase relationship between the reference bit stream and this second bit stream. The phases of the reference bit stream and the second bit stream are compared to determine a window containing the beginning of each bit of the second bit stream. The time-delay, if any, to be applied to the second bit stream is determined on the basis of this window. A switching device is commanded by a signal corresponding to this time-delay to insert into a transmission line carrying the second bit stream a time-delay device imposing the necessary time-delay. As a result, the beginning of each bit of the second bit stream is situated in the reference window.