A gate electrode having an insulating top layer as well as insulating sidewall spacers permits the source and drain regions to be electrically contacted through windows directly above the source and drain regions formed in a window pad layer. The window pad layer may also be used as a sublevel interconnect.

A molybdenum mask is used instead of a photoresist mask in defining and etching an oxide-encapsulated molybdenum gate in a VLSI manufacturing method. The molybdenum mask is first defined by a photoresist mask, then the photoresist is removed, leaving the molybdenum mask. A long over etch can then be tolerated so that oxide filaments can be avoided; this would be otherwise unreliable due to damage to photoresist during the over etch.

A method of manufacturing a semiconductor device, in particular a contact portion of the wiring of the device. An insulating layer is formed on a semiconductor substrate, a contact hole is formed on the insulating layer by etching, and a first conductive layer having hollows is formed on the insulating layer and in the contact hole. Next, a flattening layer is formed to flatten the surface of device structure, and a part of the first conductive layer is exposed by etching the flattening layer to permit a part of the flattening layer to remain in hollows of device structure. Next, a second conductive layer is formed on the remaining flattening layer and the exposed part of the first conductive layer, and is connected to the semiconductor substrate.

An intermediate structure in the fabrication of a metal-oxide semiconductor field-effect transistor is made from a substrate of p+ silicon having an elongate insulated gate structure on its main face. First and second areas of the main face are exposed along first and second opposite sides respectively of the gate structure. Donor impurity atoms are introduced into the substrate by way of at least the first area of the main face, to achieve a predetermined concentration of electrons in a region of the substrate that is subjacent the first area of the main face. The gate structure is opague to the impurity atoms. A sidewall of silicon dioxide is formed along the first side of the gate structure, whereby a strip of the first area of the main face is covered by the sidewall and other parts of the first area remain exposed adjacent the sidewall. Donor impurity atoms to which the gate structure and the sidewall are opaque are introduced into the substrate by way of the portion of the first area that is exposed adjacent the sidewall. A layer of polysilicon is disposite over the portion of the first area of the main face that is exposed adjacent the sidewall. This layer extends up the sidewall and over the gate structure. A layer of a polymer material is formed over the layer of polysilicon to a substantially uniform height over the main face. The height of the free surface of the layer of polymer material is at least as great as the maximum height of the layer of polysilicon over the gate structure. The polysilicon at a height that is at least as great as that of the gate structure is then removed.

A method of fabricating FETs to reduce parasitics. Contact is made to the source and drain regions through a polycrystalline silicon runner which is aligned with the edge of the gate electrode. This is accomplished by providing a multi-level electrode structure including a gate electrode and depositing the polycrystalline silicon layer over the device. The polycrystalline silicon is rendered selectively removable in the portion overlying the gate electrode. When this portion is removed, the remaining polycrystalline is aligned with the gate.