This disclosure relates to a control system for transferring binary words from a memory system. One thirty two bit double word may be loaded into a selected two of four sixteen bit registers. As a first of the two selected registers is read, another thirty two bit word may be loaded into the unselected registers. Alternatively, sixteen bit single words may be loaded into and read from the registers. When a word has procedural information, it is read from the registers onto a CPU control bus via a multiplexer. When a word is an encoded computer instruction to the CPU, it is read from the registers into a logic unit via a multiplexer. A decoded instruction from the logic unit is read onto a CPU control bus.
A ping-pong data buffer mechanism for transferring data from one data bus to another data bus is described. This mechanism includes a dual port storage mechanism having a single storage array and two independent ports with each port having its own separate data, address and control lines. Write circuitry is coupled to one of the independent ports for receiving data from one of the data buses and storing it into a first portion of the storage array. Read circuitry is coupled to the other of the independent ports for simultaneously reading data from a second portion of the storage array and supplying it to the other data bus. Mode control logic is provided for enabling the storing and reading functions of the first and second portions of the storage array to be interchanged back and forth from time to time so that data may be read from one portion while data is being stored into the other portion and vice versa. In a second embodiment, a pair of dual port storage mechanisms are utilized for facilitating the transfer of data from a wider data bus to a narrower data bus or vice versa.
Methods and apparatus are disclosed for realizing an integrated cache unit (ICU) comprising both a cache memory and a cache controller on a single chip. The novel ICU is capable of being programmed, supports high speed data and instruction processing applications in both Reduced Instruction Set Computers (RISC) and non-RISC architecture environments, and supports high speed processing applications in both single and multiprocessor systems. The preferred ICU has two buses, one for the processor interface and the other for a memory interface. The ICU support single, burst and pipelined processor accesses and is capable of operating at frequencies in excess of 25 megahertz, achieving processor access times of two cycles for the first access in a sequence, and one cycle for burst mode or piplined accesses. It can be used as either an instruction or data cache with flexible internal cache organization. A RISC processor and two ICUs (for instruction and data cache) implements a very high performance processor with 16k bytes of cache. Larger caches can be designed by using additional ICUs which, according to the preferred embodiment of the invention, are modular. Further features include flexible and extensive multiprocessor support hardware, low power requirements, and support of a combination of bus watching, ownership schemes, software control and hardware control schemes which may be used with the novel ICU to achieve cache consistency.
A system device of a PC, XT or AT type computer having an ISA bus is provided with a dynamic 32-bit bus by packing circuits or PACs (142, 152) located on user add-on cards. Each PAC includes a state machine (200) which controls four tag registers (210, 211, 212, 213), four input data registers (220, 221, 222, 223), four output data registers (240, 241, 242, 243), and an output multiplexer (250). The four tag registers are for storing a byte-high enable signal BHEN and system address bits SA[1:0] associated with bytes, words, and doublewords presented to the PAC during bus write cycles. The four input data registers are for storing the bytes, words, and doublewords presented to the PAC during bus write cycles. These bytes, words, and doublewords are steered to appropriate bit positions in the input data registers by four steering circuits (214, 215, 216, 217), which are controlled by the platform type signal CR2B2.sub.-- 1 and by the output of a decoder decoding the outputs of the tag registers. The four output data registers are for storing outputs of the four input registers received through an encoder (234). The output multiplexer is for selecting an output of one of the output registers. For AT-type platforms, up to two adjacent words are packed into one 32-bit doubleword for output. For PC and XT type platforms, up to four adjacent bytes are packed into one 32-bit doubleword for output. The PACs are also compatible with computers having EISA or PCI buses. During 32-bit EISA or PCI bus cycles, the input doubleword is furnished as the output doubleword.
A method for translating information of balancing loads among bus segments to provide a load balanced bus system. The method includes the steps of displacing bus connection balancing loads from a least significant bit location of a digital device bus by an offset factor and translating information between the balancing load and a the digital device bus within a switch by circularly shifting the information by a number of bits equivalent to the offset factor.
A microcomputer system memory architecture and method allows the system memory to provide data access at high speeds in a burst mode. The architecture and method utilizes a system memory controller capable of performing the addressing of the system memory. The microprocessor and the system memory communicate via a high speed host bus. The system memory is comprised of multiple 64-bit system memory buses to permit high speed data transfer to the microprocessor in a burst mode without the need for an external cache.
