A circuit for controlling data transfer handshake protocol so that certain protocol events may occur prior to or simultaneously with the completion of a proceeding protocol event, and the ultimate results of the pending protocol event may be determined at a later time. In one embodiment of the invention a CPU operates to transfer data (either receive or send) between itself and an I/O channel every five processor clock cycles. At the beginning of each set of five clock cycles the CPU places data on the data bus and generates a transfer request (CPU-XFR) signal whenever it receives a data accepted (DATA-ACC) signal indicating that a previous data transfer has occurred. The CPU-XFR signal is generated regardless of whether or not the previous data transfer is complete at the time. The data transfer normally is completed one clock cycle after the CPU-XFR signal is generated, and at that time a transfer complete signal is generated. If the transfer complete signal is not generated, a transfer inhibits signal is generated for inhibiting the generation of the succeeding DATA-ACC signal and hence the next CPU-XFR signal.

An apparatus in a computer system for handling data transfer between a first data processing system and a second data processing system is described. The apparatus includes a buffer for storing data received from the first system at a first data transfer rate and then transferred to the second system at a second data transfer rate. The buffer generates a first indication signal when substantially full and a second indication signal when substantially empty. A first counter counts a first predetermined time interval when receiving the first indication signal, and generates a third indication signal when reaching the first predetermined time interval. The first counter stops counting and returns to an initial state when not receiving the first indication signal. A second counter counts a second predetermined time interval when receiving the second indication signal, and generates a fourth indication signal when reaching the second predetermined time interval. The second counter stops counting and returns to the initial state when not receiving the second indication signal. A first logic causes the first system to delay sending the data to the buffer when the first counter receives the first indication signal to count toward the first predetermined time interval, and causes the first system to stop sending the data when the first counter generates the third indication signal. A second logic causes the second system to delay receiving the data from the buffer when the second counter receives the second indication signal to count toward the second predetermined time interval, and causes the second system to stop receiving the data when the second counter generates the fourth indication signal.

In an information processor, input interface units (161, 162) are connected to one ring data bus (191) through jointing units (201, 202) and data processing units (181 and 185) are connected to the ring data bus (191) through jointing units (203 through 206) and branching units (221 through 224). Data processing units (183 through 187) are connected to the other ring data bus (192) through jointing units (207 through 210) and branching units (225 through 228) and output interface units (171, 172) are connected to the other ring data bus (192) through branching units (229, 230). The ring data buses (191, 192) propagate the respective in data through the input interface units (161, 162) while storing such data, and processing the data in any of the data processing units to provide outputs to any of the output interface units (171, 172). Thus, since the data is transmitted through the ring data buses ( 191, 192) while being held in the data buses, there is no necessity to provide a memory for temporarily storing the data in each data processing unit. In addition, for a large scale integration of a system, it is easy to integrate each unit in a high density.

An asynchronous communications element which incorporates user-selectable FIFOs both as transmitter and receiver buffers to reduce CPU interrupt overhead. The asynchronous communications element includes a receiver shift register which receives serial data transfers from a communication station, a receiver FIFO which receives parallel data transfers from the receiver shift register for transfer to the CPU, a transmitter FIFO which receives parallel data transfers from the CPU, and a transmitter shift register which receives parallel data transfers from the transmitter FIFO for serial transfer to the communications station. A transmitter time delay eliminates multiple interrupts for a transmitter FIFO "empty" condition that has already been indicated to the CPU. Programmable interrupt levels on the receiver FIFO, together with a receiver FIFO that continues to fill beyond the programmed interrupt level, allow adjustments for variable CPU latency times. A receiver time delay interrupt indicates to the CPU that there are data characters in the receiver FIFO which have not reached the programmable trigger level, but which exceed specified time limit conditions. The receiver and transmitter FIFOs may be both individually and simultaneously disabled; a single-bit register flag indicates their status.

An asynchronous communications element which incorporates user-selectable FIFOs both as transmitter and receiver buffers to reduce CPU interrupt overhead. The asynchronous communications element includes a receiver shift register which receives serial data transfers from a communication station, a receiver FIFO which receives parallel data transfers from the receiver shift register for transfer to the CPU, a transmitter FIFO which receives parallel data transfers from the CPU, and a transmitter shift register which receives parallel data transfers from the transmitter FIFO for serial transfer to the communications station. A transmitter time delay eliminates multiple interrupts for a transmitter FIFO "empty" condition that has already been indicated to the CPU. Programmable interrupt levels on the receiver FIFO, together with a receiver FIFO that continues to fill beyond the programmed interrupt level, allow adjustments for variable CPU latency times. A receiver time delay interrupt indicates to the CPU that there are data characters in the receiver FIFO which have not reached the programmable trigger level, but which exceed specified time limit conditions. The receiver and transmitter FIFOs may be both individually and simultaneously disabled; a single-bit register flag indicates their status.