Disclosed is a method for transferring data between at least one direct access storage device in a media console and devices in a system unit. The system unit is separate from the media console and includes a microprocessor coupled to a local bus and an expansion bus. An electrical connector having one end coupled to the media console and another end coupled to the system unit is used for electrically connecting device(s) in the console to devices in the system unit. The method includes the steps of monitoring the expansion bus with a first interface in the system unit to determine when a bus cycle initiated by a device in the system unit is directed to the direct access storage device and transferring data from the expansion bus to the direct access storage device via the electrical connector and a second interface in the console when a bus cycle is directed to the direct access storage device.

Disclosed is a personal computer system that includes a media console coupled to a system unit with a multi-conductor cable. The media console includes a direct access storage device having an opening for receiving a removable storage medium. The system unit is separate from the console and includes a microprocessor coupled to a local bus and an expansion bus, a non-volatile storage device coupled to the local bus and a power supply for supplying power to the system. The cable has one end coupled to the console and another end coupled to the system unit for electrically connecting devices in the console to devices in the system unit. The system unit has a first interface coupled to the expansion bus and the cable, and the console has a second interface coupled to the cable and the direct access storage device in the console. The first interface is operative to (1) determine when a bus cycle initiated by a device in the system unit is directed to the direct access storage device in the console and (2) transfer data from the expansion bus to the direct access storage device via the cable and the second interface when a bus cycle is directed to the direct access storage device.

An IC memory card for storing picture data, character data or similar data. The memory card has an input/output section connectable to a host, a storage implemented by a semiconductor memory, and a controller for writing or reading data out of the storage. The input/output section has a data terminal for receiving an address signal and a data signal each being made up of a plurality of blocks continuously, an address/data discrimination terminal for receiving a bilevel signal for discriminating the address signal and data signal fed to the data terminal from each other, a read/write discrimination terminal for receiving a bilevel signal for discriminating the read-out and write-in of data from each other, and a bus clock input terminal for receiving a bus clock synchronous to each block of the address signal or each block of the data signal.

Using a variable-duration clock circuit, together with programmable duration control to alter the clock waveform within strict rules, permits the programmer to arrange appropriately short durations for short data transfers, and to arrange appropriately longer durations for longer data transfers in an array processor of myriad processing elements. There is no need to allow sufficient time in every clock cycle for worst case data transfer between remote processing elements. The clock waveform has three recognizable edges (A,B,C) regardless of loss of sharpness during its travel to the various processing elements. The convention that three skew-sensitive activities, READ, WRITE and OPERAND SUPPLY conform to respectively assigned edges as follows: A=READ; B=OPERAND SUPPLY; C=WRITE (Read next) The processing elements synchronize with the clock waveform, which is optimized for the instructions of the program being executed. There is no time wasted allowing for worst case data transfers possible in certain instructions but not possible in other instructions.

Disclosed is a bus expansion unit for extending the bus of a computer system which has an asynchronous bus cycle. The bus expansion unit includes an asynchronous state machine which uses a delay line to determine some of its states. The bus expansion unit recognizes the address and bus status and holds or latches a select signal. In addition, the bus expansion unit delays the -CMD signal until the peripheral has the opportunity to place valid data on a bus channel. In addition, the bus expansion unit includes an arbitration circuit for the peripheral attached thereto.