A phase synchronization circuit of a phase lock loop having a phase comparator, a loop filter or a low-pass filter and a voltage controlled oscillator controlled by output of said loop filter has been improved by a phase comparator having the hysterisis characteristics in which one of a pair of output levels is provided for each input phase difference according to phase error direction, except in the vicinity of a stable point of phase.

A method for simple synchronization of a receiving device to a transmitting device for a transmission of a dispersed-energy QPSK signal. The signal is composed at the transmitting end of two mixed products, the mixed product of an I signal and a transmitted carrier and the mixed product of a Q signal and the transmitted carrier shifted through 90.degree.. In order to synchronize the received carrier to the transmitted carrier without any problems, it is proposed that an amplitude of an SQ signal be measured at the time of the zero crossing of the rising flank of an SI signal, and that an amplitude of the SI signal be measured at the time of the zero crossing of the falling flank of the SQ signal. The measured values are a measure of a discrepancy from synchronicity between the received carrier and the transmitted carrier, and that the frequency of the received carrier be varied until the amplitude of an error signal obtained from this measurement is zero. The measurement is carried out with the smallest possible number of measured values.

A phase comparator circuit for use with a digital phase-locked loop which can be programmably altered to provide phase comparisons either on the leading edge or leading and trailing edges of the phase-locked loop output signal, to provide an increased operating bandwidth capability to the phase comparator circuit. The phase comparator circuit can be configured to cooperate with a multiple frequency digital phase-locked loop such that the results of a phase comparison will be delayed until a frequency adjustment has been completed.

A unitary phase and frequency adjust network for use in a multiple frequency digital phase-locked loop circuit is described. The unitary phase and frequency adjust network utilizes a single circuit to effect both phase and frequency adjustments. The multiple frequency digital phase-locked loop effects phase adjustments by selectively combining or subtracting a reference clock signal with a derived programmable clock signal thereby generating a composite digital phase-locked loop clock signal. The phase and frequency adjust network effects frequency shifts by selectively adding or subtracting pulses from the composite clock signal at a rate determined by a programmably controlled clock signal.

A phase detector generates a first output signal if a feedback clock signal leads a reference clock signal by more than a first time. The phase detector generates a second output signal if the feedback clock signal lags the reference clock signal by more than a second time. If the feedback clock signal either leads the reference clock signal by less than the first time or lags the reference clock signal by less than the second time, neither output signal is generated. The phase detector may be used in a delay-lock loop in which the first and second output signals increase or decrease a delay of the reference clock signal by respective first and second delay increments. In such case, the each of the first and second delay increments should be less than the sum of the first and second times.