An instruction processor suitable for use in a reduced instruction-set computer employs an instruction pipeline which performs conditional branching in a single processor cycle. The processor treats a branch condition as a normal instruction operand rather than a special case within a separate condition code register. The condition bit and the branch target address determine which instruction is to be fetched, the branch not taking effect until the next-following instruction is executed. In this manner, no replacement of the instruction which physically follows the branch instruction in the pipeline need be made, and the branch occurs within the single cycle of the pipeline allocated to it. A simple circuit implements this delayed-branch method. A computer incorporating the processor readily executes special-handling techniques for calls on subroutine, interrupts and traps.

Encachement apparatus comprising a plurality of frames which include registers for storing data, one of which frames is selected as a current frame, the encachement apparatus responding to a key for outputting data from the registers in the current frame. The current frame is selected from a succession of frames and during a call operation a new current frame is selected as the frame following the current frame and during a return operation a new current frame is selected as the frame preceding the current frame.

Encachement apparatus for use in a processing unit which is responsive to data items which include first and second component values, while values change in response to first and second operations, respectively, of the processing unit. The encachement apparatus comprises first and second caches for storing and outputting first and second component values of such data items which values are combined to form the data items involved.

An address environment storage unit for a stack-oriented data processor for operating in data sets arranged as structured blocks, or nested pushdown stacks. The address environment storage employs a plurality of sets of display registers such that the current set of display registers does not have to be updated each time the processor moves to a different area of data in memory. The programmer only needs to provide a designation of a lexical level in a particular stack and the offset value from the base of the particular activation record in that stack for addition to obtain actual memory address. When the processor executes a procedure enter operator that calls for a new section of memory in which to operate, a display pointer is changed to point to the set of display registers provided for accessing that new area of memory.

Encachement apparatus consisting of first and second caches responsive to first and second keys, respectively, for outputting first and second data therefrom. In one embodiment, the second cache which includes a stack having a plurality of frames, outputs data contained in a current frame thereof in response to a second key which is obtained from the first cache. The data outputted from each cache is received substantially simultaneously at a combiner which combines such data to produce the desired third data from the dual cache system.