A simple method and apparatus for generating approximate sine waves is described. A digital accumulator or adder is driven at a basic counting rate to accumulate increments representative of phase with the total sum representative of total phase angle of a sine wave. The output is periodically sampled and the value is converted into an analog output voltage in a normal D to A converter. A straight line ramp voltage approximation to the sine wave function is created as the result. The accumulator operates in this fashion until a total phase angle of approximately 45.degree. is accumulated. Then accumulation value additions are then accorded 1/2 their usual significance until 671/2.degree. of total phase angle are accumulated. Then accumulation is then at 1/4 the basic significance accorded to increments until 90.degree. is reached. The symmetry of the sine wave allows the 0.degree. through 90.degree. samples to be used to generate the full 360.degree. wave form by simple inversion or reverse counting of the counter and inversion of the algebraic sign as necessary. A binary slope approximation to the sine function is achieved by this technique. A series of straight line slopes with a slope of 1, 1/2 and 1/4 are utilized to approximately track a true sine function. The breaks in slope occur in a binarily related fashion to a 90.degree. quarter cycle at 90.degree./2 and at 90.degree./4. These simple binary relationships allow the sine function to be approximated very easily by discrete logic and simple binary counters or parallel adders or by the equivalent counting in registers of a microprocessor. The resulting output is applied to a D to A converter to derive the output analog voltages.
A circuit for generating an analog sine voltage from a digital phase input (11) employing a memory (13) storing sine and cosine values and a correction value for each phase and first and second digital-to-analog converters (DACs) (19,21). For each digital phase input (N), selected sine and cosine values are combined and the result is read out to the first DAC (19), which generates an analog sine approximation voltage. A corresponding correction value is simultaneouosly read out to the second DAC (21), whose output is scaled by an attenuator (23) to provide a correction voltage for correcting the deviation in the output voltage of the first DAC (19) from the ideal sine voltage value.
A direct digital synthesizer that outputs at least a predetermined output frequency related signal from a received digital signal, K, with minimum spurious signal levels. A storage device stores an initial phase value of the digital signal, K, and provides the initial phase value on an output thereof. An adder is provided having a first input for receiving the digital signal, K, having a second input and having an output which provides a summation of signals received on the first and second inputs. A latch has a first input connected to the output of the storage device, has a second input connected to the output of the adder and an output connected to the second input of the adder. The latch also has a third input for receiving a select signal for selecting between receiving on the first and second inputs of the latch. A control circuit provides the select signal in response to one of a plurality of predetermined parameters. The output frequency related signal is provided on the output of the latch. One or more detectors identify a power interrupt of the direct digital synthesizer or a change in the digital signal, K, and provides a detect signal to the control circuit. When a power interrupt or change in K is detected, the control circuit causes the latch to first receive the initial phase value on the first input thereof and then switch to the second input thereof for subsequent operations.
A circuit for generating successive points on a sine wave using the Coordinate Rotational Digital Computer (CORDIC) algorithm. An angle memory and an amplitude memory store respective angle and amplitude values from which a CORDIC logic processor calculates a point on a sine wave. A frequency memory stores an increment value unique to the frequency of the sine wave to be formed, and an arithmetic logic unit adds the increment value to the stored angle value after the point on the sine wave is calculated. The CORDIC logic processor then calculates the next point on the sine wave from the incremented angle value. A digital-to-analog converter may be used to provide an analog output signal. For generating multi-tone signals, the angle, amplitude and frequency memories are configured to store a plurality of angle, amplitude and increment values, and an address memory is connected to each memory for simultaneously addressing them. A periodic counter is connected to the address memory and cyclically selects the addresses in the address memory to be used for addressing the angle, amplitude and frequency memories. The multi-tone signals are then produced by serially time-multiplexing the CORDIC processor among the frequencies.
A digital synthesizer is provided with an address converter means for converting a phase value in the region of small amplitude change all to a predetermined value, utilizing the characteristics of a sinusoidal function. In addition, a digital synthesizer is provided with a second address converter for converting the phase value in a range of 0.degree..about.360.degree. to a phase value of 0.degree..about.90.degree. and an output data inverter inverting the memory output in response to the phase value. By converting a phase value in the region of a small amplitude change to a predetermined value, the amplitude value to be stored in the memory can be reduced by that degree, and reduction in the memory capacity and reduction in the power dissipation are achieved. Furthermore, by converting the phase value in a range of 0.degree..about.360.degree. to a phase value of 0.degree..about.90.degree. utilizing symmetry of the sinusoidal function, the amplitude value to be stored in the memory can be reduced to one-fourth, thereby further reduction in the memory capacity and further reduction in the power dissipation are achieved.
A circuit for providing a mirrored version of a preselected transfer function includes a circuit having the preselected transfer function coupled to receive a signal modulated by a signal that is to experience the mirrored transfer function. The modulated signal at the output terminal of this circuit is mixed with a signal at a frequency that is greater than the carrier frequency of the modulated signal. The signal resulting from this mixing operation then is low pass filtered to provide the desired mirrored response.
