A motor driving circuit comprising a pulse generating circuit for generating plural types of pulse trains, a modulation pulse generating circuit connected to the pulse generating circuit, a semiconductor driving circuit connected to an output of the modulation pulse generating circuit for providing operating power to a motor winding, a detecting circuit connected to the driving circuit for detecting a voltage induced in the motor winding, and a counting circuit connected to the detecting circuit. The detecting circuit has means for setting reference levels, detects the voltage induced in the motor winding in accordance with the reference levels during the time the semiconductor driving circuit is non-conducting, and sends control signals for regulating a next produced modulation pulse width to the counting circuit, and the modulation pulse generating circuit shapes the modulation pulse from the plural types of pulse trains of the pulse generating circuit in accordance with outputs of the counting circuit so as to drive the motor uniformly.
A circuit for generating a pulse-like timing signal driving a stepping motor which is used to drive for example a magnetic tape to run in an audio tape or video tape recording and reproducing apparatus. A rewritable memory stores output pattern data and time information for generating the timing signal. This timing signal generating circuit comprises a rewrite control circuit responsive to an operation mode instructing signal, for performing a predetermined operational processing on basic pattern data and basic time information and storing the resulting output pattern data and uniquely related time information in the rewritable memory. This timing signal generating circuit further comprises a circuit for generating a clock signal having a predetermined cycle, a counter for counting this clock signal and a circuit for sequentially reading out the time information from the rewritable memory, detecting match between the read-out time information and count value of the counter, and outputting the output data stored in the rewritable memory corresponding to the time information for which match is detected, as the timing signal. This output circuit comprises a circuit for continuously outputting the present output data until another match is detected between the subsequently read-out time information and the count value of the counter.
A speed controller for a DC motor minimizes speed droop and load droop through pulse width or frequency modulation. The controller provides an extra power increase upon engine starting or whenever a heavier load is temporarily encountered. The control circuit also has a current limiter, overload indicators, and a battery recharger. The controller is very inexpensive, primarily because all of the timing components are contained on a single integrated circuit timer chip such as a 556 timer. The controller contains other features, including a circuit for limiting the pulse width of the control signal from the pulse width modulator.
