A frame transfer type solid-state imaging apparatus has a matrix of pixels which store information charges corresponding to a received image. The information charges are moved from the pixels to vertical transfer registers, and then to a horizontal transfer register, prior to being stored. A timing control circuit generates a vertical scan timing signal and a horizontal scan timing signal using a divided clock signal. A horizontal drive circuit generates a horizontal transfer clock using the divided clock signal and the horizontal scan timing signal. The horizontal transfer clock is used to move the information charges from the vertical transfer registers to the horizontal transfer register. A vertical drive circuit generates a vertical transfer clock using a reference clock signal and the vertical scan timing signal. The vertical transfer clock is used to move the information charges from the pixels to the vertical transfer registers. The divided clock signal is generated by dividing the reference clock signal by a predetermined ratio, such that the divided clock signal is longer than the reference clock signal. By generating the vertical transfer clock using the reference clock, and not the longer, divided clock, the resulting image does not have an increase in smear components.

An X-Y addressable imager utilizes a gate connection of a source-follower-connected MOSFET to isolate inherent capacitance of each horizontal signal line of the imager from a vertical signal line that couples the MOSFETs to a common output circuit, including a load resistor for the source followers. In one embodiment the horizontal signal lines are assigned to different groups, and each group is coupled through a different one of plural vertical signal lines to the common output circuit. At least one multiplexer couples one vertical signal line at a time to the common output circuit. Also shown is imager array scanning logic for effecting variable integration of array pixels.

The effective light incident upon pixels of an X-Y addressable imager is controlled by electrically controlling the effective photonic charging time of each pixel in each frame time of operation. The horizontal signal lines of the imager are assigned to different groups, and each group is coupled through a different one of plural vertical signal lines to a common output circuit. A multiplexer couples one vertical signal line at a time to the common output circuit. Imager array scanning logic is provided for recurrently selecting pixels of two of the horizontal signal lines at a time, but connecting only one of them to its vertical signal line at that time, for effecting variable integration by array pixels.