Duplicated circuit arrangement comprising a main processor (30) and its P bit data bus (44), and two identical redundant devices (21:22), each device is comprised of a processing element (23;35) performing the same task in parallel on a P bits word, and send/receive circuits (24,25;36,37) controlled by the main processor through lines (SR11 to SR22) to transmit said word to and from said main processor. For each device, the send/receive circuits are split into two parts. Send/receive circuit of the first device (21) is split in two parts (24, 25); the first part (24) handles the P/2 Most Significant Bits (MSB's) and the second part (25) handles the P/2 Less Significant Bits (LSB's). In normal operation, during the transmission step, only the first part (24) is allowed to send bits on one half (33) of the data bus (44). Symmetrically send/receive circuit of the second device (22), is also split in two parts (36, 37); the first section (36) handles the P/2 Most Significant bits (MSB's) and the second part (37) handles the P/2 Less Significant Bits Z(LSB's); only the second part (37) is allowed to send bits on the other half (34) of the data bus (44). Therefore, the data bus driving effort is equally shared between the two devices, the maximum number of simultaneous switching is P/2 for each device. This reduction allows greater transmission speed on large busses.

A method and an apparatus for controlling an elevator is equipped with a deck-distance drive machine which by reference to positional information adjusts the distances between the individual cars in a common car sling in such a way that each car can stop at the corresponding floor accurately, i.e. without forming a step. Measured values of floor position are stored in memories and periodically updated so as to detect any changes such as, for example, building settlement. Based on this data the necessary deck-distances are calculated which are necessary for all the cars to stop without any of them forming a step. Furthermore, the method and the device can be correspondingly extended for a multi-decker elevator and for any type of control (conventional control, destination call control, etc.).

A multiprocessor programmable interrupt controller system has an interrupt bus, distinct from the system (memory) bus, for handling interrupt request (IRQ) related messages. Each processor chip has an on-board interrupt acceptance unit (IAU) coupled to the interrupt bus to accept IRQs and to broadcast IRQs that it generates. I/O device interrupt lines are connected to one or more interrupt delivery units (IDUs) that are each coupled to the interrupt bus to broadcast I/O-generated IRQs. The interrupt bus is a synchronous three-wire bus having one clock wire and two wires for data transmission. Arbitration for control of the interrupt bus by the IAUs and IDUs uses one of the data wires. Lowest priority IRQ delivery mode uses a similar one-wire arbitration procedure for determining which IAU has the lowest current priority task running in its associated on-chip processor. A modification to this procedure also provides uniform distribution of IRQs to eligible processors. The actual servicing of the IRQs is done via the system bus. IAU acceptance logic is minimized by allowing retry of a delivered message when the acceptance latches are full. The increase in interrupt bus traffic due to retry is minimized by controlling the time intervals between rebroadcasts of unaccepted IRQs. Exponential timers control this interval so that each succeeding interval is a multiplicative factor, typically 2, greater than the preceding interval.

A method of maintaining network protocol timers in data structures associated with different respective processors in a multi-processor system. The timers accessed by a respective one of the processors include timers of connections mapped to the processor.

A multi-processor system includes an interrupt bus used for arbitrating among eligible processors to determine which processor is to service of an interrupt request. The interrupt bus comprises wired-OR connection data lines that are used for arbitration. A local interrupt controller that handles the acceptance of interrupt request messages on the interrupt bus is associated with each processor. To minimize interruption of high priority tasks, interrupts can be accepted by the processor in the system that is currently running the lowest priority task. An arbitration protocol governs the interrupt bus and determines the lowest priority processor. The arbitration protocol includes choosing one among the lowest priority processors by means of a random priority scheme that uses an arbitration ID that is updated with each message.