An input/output system for a processor of the kind in which a processor module has a central processing unit, a memory, an input/output channel, and a plurality of device controllers for controlling the transfer of data between the processor module and the peripheral devices includes a star poll connection in which each device controller is provided with a signalling means for signalling its identity in response to a poll operation, independently of other similarly connected device controllers such that any number of device controllers can be failed or powered off without affecting the polling of the other device controllers. The data lines in an input/output bus are used both to transmit data and to transmit signals to reduce the total number of lines needed to connect the device controllers to the channel in the star poll connection. The system is a fault tolerant system which includes an enable bit in the port of each device controller. The bit can be reset to prevent that device controller from transmitting spurious signals which could interfere with interrupt requests being transmitted to the channel by other device controllers so that a failed device controller can be effectively removed from the system. A rank line arrangement is utilized in the priority selection scheme so that an additional group of controllers can be added in a way which requires the use of only one more line in the input/output bus and still allows each device controller to respond independently to poll operations.
This application is a continuation of application Ser. No. 06/147,310 filed May 6, 1980 (now abandoned) which is a division of application Ser. No. 721,043 filed Sept. 7, 1976, now U.S. Pat. No. 4,228,496.
A device interface module provides multiple concurrently operating data transfer channels between multiple groups of peripheral devices and ad multiported buffer memory which communicates via an interface bus to other external modules of a computer system.
In a multiple-CPU, dynamic path allocation environment. The environment, several devices, such as input/output (I/O) devices, may be accessed through one of a plurality of dynamically configured paths from the CPU. Each path includes a channel, from the CPU, connected to a director. The director, in turn, is connected through respective control module interfaces, to a plurality of control modules, which control modules are used to access a string of devices. The connection method, carried out under control of the director, includes simultaneously polling all of the control modules to determine if any have devices attached thereto that are ready to be connected to the CPU. A response from the control modules, all received simultaneously at the director, identifies the CPU channel through which the connection is to be made. The specific address of the device to be connected is then determined, and the desired connection from the CPU to the device is completed.
A search engine system (100) is disclosed that can include at least one content addressable memory (CAM) device (102) arranged in a cascade configuration with at least one memory device (104), such as a static random access memory (SRAM). A CAM device (102) and memory device (104) may be connected to one another by point-to-point unidirectional connections. Command data issued by a device, such as a network processing unit (NPU) (110), can flow through all devices beginning with a CAM device (102) and eventually to a memory device (104). A memory device (104) can compare its own current result data with that of a previous device in a flow (such as another RAM device), and generate an output response.
The host adaptor packages 4 and the disk adaptor packages 6 which constitute the magnetic disk subsystem 1 are connected to the common bus 3 consisting of a data bus, a control bus, and a power line in the hot replacement ready state. The packages 4 and 6 have the control means 11 and the clock generator 14 and when a failure occurs in respective packages, the package replace controller 13 mounted in the control means 11 executes the blocking processing for the bus driver 15 and the clock generator 14. If this occurs, the clock generator 14 enters the stopped state, so that the circuit in the package enters the reset state and the package function is stopped, that is, the package enters the blocked state. As a result, hot replacement of the closed package can be executed without affecting the operation of the system.
A field bus system may be used in which transmission ability of the system can be maintained even if communication error occurs due to noises or failure of a transmission line. The system can be easily shifted at a lower cost from a conventional system to the field bus system without degrading the high reliability thereof. The transmission line is constituted by a multiple-cable transmission line having at least three transmission cables. An external power supply supplies power to field devices through a pair of transmission cables of the multiple-cable transmission line. The field devices are connected to the transmission cables through a transmission line switching unit constituted by a plurality of rectifier elements, so that the field devices are supplied with current flowing in one predetermined direction when any of the pairs of transmission cables is selected. The external power supply monitors a failure of a currently used pair of transmission cables and, upon detection of failure of the currently used pair of transmission cables, the failed pair is replaced by a normal pair of transmission cables such that the field devices are continuously supplied with power.
