An interface, between a display monitor and a source of image information for display as pixels at display locations of the monitor, the interface comprising: a monitor input terminal for receipt of image information for display on the monitor; a refresh memory for storing image information at memory locations corresponding to the display locations of the monitor; a device for sequentially reading the image information from the memory locations of the refresh memory to the monitor input terminal for display at the corresponding display locations of the monitor; a device for storing new image information for one of the memory locations of the refresh memory; and a device for replacing sequential reading of the image information from said refresh memory at the one of the memory locations with: (i) reading of new image information from the new information store to the monitor input terminal for display of the new image information at the discrete display location of the monitor corresponding to the one of the memory locations, and (ii) writing the new image information from the new information store to the one of the memory location of the refresh memory. A related method is also provided.

An image reproduction interface disposed between a CPU, and a display device for reproducing an image based on code signals from the CPU corresponding to multiple image elements. The interface comprises a random-access memory for temporarily storing the code signals, and a multiplexor for selecting, for a first period, an address bus for the CPU to address the memory for storing therein the code signals, and for a second period, a refresh address bus for a controller of the display device to address the memory for reading out therefrom the code signals to reproduce the image. A sum of said first and second periods is equal to an interval at which the image elements are reproduced, whereby both storage and retrieval of the code signals into and from the memory may be effected within each reproduction interval in a time-sharing manner, thus reducing an idle or waiting time of the CPU and increasing a rate of updating the image on the display device.

An apparatus for the control of an access to a video memory comprises a memory width register having a content of a number of dot periods by which an access timing is determined to address a video memory. Therefore, an access timing is easily controlled dependent on a memory speed of the video memory only by changing the content of the memory width register. When the video memory is accessed during a display cycle of the video memory, video data may be stored in a buffer memory, and transferred from the buffer memory after the display cycle is finished.

A character memory of a data display arrangement is divided into a plurality of separate memory sections which are available to provide characters for display only for respective sub-areas of a display screen. The invention is especially suited to providing high resolution character-based displays using so-called dynamically redefinable characters sets. A memory map MM containing the memory sections is addressed by a counter COU. A latch L2 initially sets the counter COU to the address of the first memory section. During each line scanning period a .div.2 divider DV is responsive to character column pulses CP to step the counter COU to address a new memory section address evey second character position. At the end of each line scanning period line pulses LP reset the counter COU to the first memory section address. In a modification, the connections of the address bus between the counter and the memory map are altered so that the addresses as actually applied to the memory sections are only changed every second (or fourth) character position so that less memory is needed.

When a contention is detected between a memory write address and a display read address in a memory circuit which stores display data, a host retry pulse generating circuit generates a display read signal and a display line data transfer signal based on a memory write clock, and supplies these to the memory circuit while supplying the display line data transfer signal to a line latch circuit. Alternatively, upon detection of the contention above, a same line re-display read processing circuit performs same line re-display read processing without moving to the next line, and supplies a display read signal and a display line data transfer signal to the memory circuit while supplying the display line data transfer signal to the line latch circuit.