An electrically programmable read only memory including a plurality of memory cells each composed of a field effect transistor having a floating gate is disclosed. The memory is featured by a test circuit which has a first circuit responding to a first control signal to raise all word lines up to a programming voltage and a second circuit responding to a second control signal to raise all digit lines up to the programming voltage. It is thereby detected whether or not electrons injected into the floating gate of the programmed memory cell are carried away during a data programming operation period.

A semiconductor memory circuit includes a plurality of memory cells arranged in an array form, a plurality of data lines for reading and writing data, a plurality of address lines each for transferring an address signal that specifies a corresponding specific memory cell, a control unit for controlling reading and writing of the data, a plurality of data input and data output terminals for inputting and outputting the data, a write enable signal input terminal to which a write enable signal for permitting writing of the data is applied, and at least one control signal input terminal to which either a cell clear signal for clearing the data stored or a cell initialization signal for performing the initialization of the data is applied. Data reading, data writing and data clearing or data initializing are performed through the plurality of data lines and the plurality of address lines. The hardware area to be occupied is reduced due to a reduction in the number of the cell transistors and also by a reduction in the number of signal lines.

A reset circuit for a CMOS memory array is disclosed wherein the voltage supply for the standard six transistor memory cell is replaced by a pair of parallel connected transistors disposed between a fixed voltage source and the memory cell. The transistors are controlled by the reset signal and are complementary in that one is n-channel and the other is p-channel. The n-channel transistor is sized to prevent excess current flow to the memory cells to prevent an excessive charge build up therein for a logical "1" representation. In addition, the n-channel transistor provides a Vtn drop thereacross to prevent current flow in the memory cells during reset.

A memory provides a byte program mode which avoids unnecessary erase and program cycles. If a byte is to be programmed, the new data to be written is first compared to the existing data in the byte. If the old data is the same as the new data, there is no need to do a conventional erase/program cycle. In such case the memory does not perform the erase and reprogram which saves much time and avoids decreasing the life of the floating gate transistors in the byte. Even if the old data is not the same as the new data, the byte may already be in the erased state. In such case the erase cycle is skipped and programming is begun.

A semiconductor memory device with a flash write function includes word lines and bit lines; memory cells connected between the word lines and the bit lines; and a flash write mode designating unit for designating a flash write mode in accordance with external control signals. The semiconductor memory device further includes an internal address generating unit which is driven during a flash write mode for sequentially generating internal address signals. The semiconductor memory device additionally has a word-line selecting unit for sequentially selecting the word lines in accordance with the internal address signals from the internal address generating unit. A preset data generating unit is further included in the semiconductor memory device for generating preset data. The semiconductor memory device further has a write unit which is driven during the flash write mode for writing data from the preset data generating unit into all of the memory cells connected to the word line selected by the word-line selecting unit, wherein the flash write operation can be effected by using the internal address and without using an external address.