In a data processing system, data is transferred between a plurality of functional devices through a shared memory without the intervention of the processor. The data transfer is controlled by a Shared Memory Access Channel (SMAC) having a pointer table storing memory addresses to control shared memory accesses and by the functional devices using device addresses, pointer identifers, indicating the pointer to be used from the pointer table, and control codes. The control codes used in the transfer include a Post code (P code), an Available code (A code) and an End of Process Code (E code). The device, from which data is transferred, is referred to as the upstream device, and the device to which data is transferred is referred to as the downstream device. The P code tells the downstream device that the upstream device has written a predetermined amount of data into a shared buffer area in the memory. The A code tells the upstream device that space is available in the buffer area for writing data to be transferred to the downstream device. The E code tells the downstream device that the data transfer operation from the upstream device has been completed.
The descrambling device comprises hardware resources (1) and first memory zones (CA1, CA2, . . . , CAn) to store at least two different access control codes for controlling the hardware resources. The device also contains an arbitration code for selecting one access control code to control the hardware resources in order to share access to the hardware resources from the access control codes. Access control codes can be downloaded in the first memory zones by means of a loader contained in the device.
A bus interface device for a data processing system in which 2M units are interconnected and exchange information bits over a bus comprising at least M lines. The device comprises a receiving circuit associated with each respective line (D0-D7) of the bus and including two flip-flops 40 and 41 that assume the voltage level on the input line at the up-going and down-going transitions of a clock signal (CLK1) and are restored at the down-going and up-going transitions of that signal. When the bits received over the bus are encoded in the NRZ code, using a bit period equal to half a period of the clock signal, OR circuit 47 provides at its output the resynchronized train of input bits received over D0-D7. The 2M units are divided into two groups, with the units in each group requesting access to the bus during either phase of a second clock signal (CLK2). When the bus is free, flip-flops 48 and 49 provide an indication of the requests for access to the bus made by the associated units.
A store and forward switching system, typically for use as a facsimile system, has a plurality of communication control units for controlling transmission and reception of data through a plurality of respective communication lines, a multiplexer for transferring data to and from a selected one of the communication control units, a hard disk for storing data, a bulk processor for reading data from the hard disk and writing data in the hard disk, a main processor for controlling the multiplexer, the hard disk, and the bulk processor, and a system bus connected to the multiplexer, the bulk processor, and the main processor. The multiplexer and the bulk processor have first and second data transfer execution units, respectively, for transferring data between the multiplexer and the bulk processor through the data transfer bus without being handled by the main processor. Since data are transferred directly between the multiplexer and the bulk processor, the main processor is freed from a burden which would otherwise be imposed by the transfer of data therethrough, and the data transfer can be effected efficiently. A data transfer bus may be connected to the multiplexer and the bulk processor for transferring data therethrough while allowing the main processor to send and receive various request and response signals through the system bus.
A traffic analyzer (16) for a local area network (10) having multiple stations (14) that exchange message packets (24) receives selected ones of the message packets (24). The analyzer (16) stores a message packet table (TABLE(0)-TABLE(6)) and generates a table pointer (P) as a function of both the source address (S) and the destination address (D) of each received packet (24). A record (S,D,N) of each received packet (24) is stored in the table entry (TABLE(P)) associated with the table pointer value (P) for the respective received packet (24), where N is equal to the number of received packets having the source address S and the destination address D.
A method and apparatus for providing high speed communications with a shared memory from both a processing control unit and a plurality of auxiliary processing devices employs a video random access memory. The processing control unit or units require random access of the memory and are operatively connected to a random access port of the video random access memory. Each auxiliary processing device is operatively connected for data transfer in a burst mode to a serial access port of the video random access memory. The method and apparatus control transfer of data to and from the serial and random access ports for effecting high speed communications at both I/O access ports of the memory. Data communication at the serial access port is in a bit serial/word parallel burst mode and occurs in one CPU cycle. The memory operates like a dynamic RAM from the random access port.
