A floating point instruction control mechanism which processes loads and stores in parallel with arithmetic instructions. This results from register renaming, which removes output dependencies in the instruction control mechanism and allows computations aliased to the same register to proceed in parallel.

A task control mechanism for maintaining a queue of ready or available processes linked together according to an assigned priority for a plurality of central processors where the processors may be assigned to the highest priority task when that processor is not busy executing some higher priority task. The task control mechanism also includes a mechanism for computing task priorities as new tasks are inserted into the queue or removed. The mechanism also maintains an event table which is really a table of event designations to be allocated to different processes upon request where the requesting processes assign a particular function or "meaning" to the event designation. The mechanism of the present invention maintains the state of such allocated events in the event table and signals the related (or "waiting") processes that an event has happened so that the particular system central processors assigned to execute those particular processes may then proceed with their execution.

A data processing apparatus includes a plurality of register blocks, each having a plurality of registers, an external memory either to save data in the register blocks or to restore data in the register blocks, and a data processing unit to execute a program using at least one of these register blocks. This data processing unit generates a first or a second signal when a subroutine call or a return occurs in the program being executed. The data processing apparatus further includes a memory interface to execute the data transfer between the register block set in the "save" or "restore" state and the external memory when the first or second signal is generated, and a register control for setting at least one of those register blocks in a state that can be used by the program executing means, and for setting a different register block into the "save" or "restore" state in response to the first or second signal.

A scbok line is connected to a register file and other units, such as an execution unit and a multiply/divide unit, in a data processing system. A mem scbok line is connected to the register file and other units, such as an instruction unit and a memory interface unit. Each unit connected to the scbok line can pull the line to indicate that it is busy. Each unit connected to the mem scbok line can pull the line to indicate that it is busy. The scbok line indicates, when asserted, that a unit or a register in the register file that is busy with a previous instruction is not available to an instruction for a register file operation. The mem scbok line indicates, when asserted, that a unit or a register in the register file that is busy with a previous instruction is not available to an instruction for a memory operation. Registers are checked concurrently with the issuing of an instruction. An instruction lacking any needed unit or a register is stopped in response to the asserted scbok line and reissued in the next cycle. Registers to be used by a multi-cycle instruction are marked busy for an instruction that is able to be executed. When a result for the multi-cycle instruction returns the registers previously marked busy are marked as not busy.

A method and device of executing a load multiple instruction in a superscaler microprocessor is provided. The method comprises the steps of dispatching a load multiple instruction to a load/store unit, wherein the load/store unit begins execution of a dispatched load multiple instruction, and wherein the load multiple instruction loads data from memory into a plurality of registers. The method further includes the step of maintaining a table that lists each register of the plurality of registers and that indicates when data has been loaded into each register by the executing load multiple instruction. The method concludes by executing an instruction that is dependent upon source operand data loaded by the load multiple instruction into a register of the plurality of registers indicated by the instruction as a source register, prior to the load multiple instruction completing its execution, when the table indicates the source operand data has been loaded into the source register. Also, according to the present invention, a method of executing a store multiple instruction in a superscaler microprocessor is provided. This method comprises the steps of dispatching a store multiple instruction to a load/store unit, whereupon the load/store unit begins executing the store multiple instruction, wherein the load store instruction stores data from a plurality of registers to memory; and executing a fixed point instruction that is dependent upon data being stored by the store multiple instruction from a register of the plurality of registers indicated by the fixed point instruction as a source register, prior to the store multiple instruction completing its execution, but prohibiting the executing fixed point instruction from writing to a register of the plurality of registers prior to the store multiple instruction completing.