A data processing system comprising an instruction control unit for controlling system operation, a storage control unit for storing data used for the system operation, and a machine check interruption portion for carrying out a machine check interruption when an error occurs during the system operation. The instruction control unit has a system control register group for storing system control data. The storage control unit has a copy register group for storing data copied from the system control data. The instruction control unit further comprises a register save state portion for copying the contents stored in the system control register group into the copy register group during the machine check interruption when an error occurs in the copy register group during the system operation. In this manner, a machine stop due to an error only in the copy register group, is prevented.

A checkpoint retry system for recovery from an error condition in a multiprocessor type central processing unit which may have a store-in or a store-through cache system. At detection of a checkpoint instruction, the system initiates action to save the content of the program status word, the floating point registers, the access registers and the general purpose registers until the store operations are completed for the checkpointed sequence. For processors which have a store-in cache, modified cache data is saved in a store buffer until the checkpointed instructions are completed and then written to a cache which is accessible to other processors in the system. For processors which utilize store-through cache, the modified data for the checkpointed instructions is also stored in the store buffer prior to storage in the system memory.

A circuit for maintaining copies of original index registers and copies of modified index registers such that in the event original copies of the index registers are needed, they may be restored. The circuit is for use in a fault tolerant system wherein in the event of a rollback, original copies of the index registers may be restored to a processor, even if some of the index registers were modified in the previous execution of a command by the processor.

An information capturing technique captures information on a processor cycle that results in a high level interrupt, such as an SMI (System Management Interrupt). A memory controller is connected to at least one processor to control a memory in response to instructions from the at least one processor. An I/O controller is connected to the memory controller to control data flow to at least one device in response to instructions from the at least one processor. Lock down logic stores captured cycle information on a processor cycle that results in interrupt.

A DMA controller with error circuitry which detects DMA error conditions is disclosed. The error circuitry causes the DMA controller to perform completion tasks before terminating a DMA transfer, advantageously providing a DMA controller which may exit gracefully upon detection of an error condition with the potential of error recovery.