In a data processing system comprising a plurality of processing elements coupled to a network, a method of single-stepping the processing elements aids in debugging the system. Only one processing element at a time is permitted to execute N steps while its data output is coupled to the network. Once it's finished executing, a time period greater than the maximum propagation delay time of the network is permitted to pass before stepping a succeeding processing element N steps. In another embodiment, the outputs of all processing elements to the network are first disabled, then all processing elements are allowed to execute N steps. Next the system is halted, and, one at a time, the data output of each processing element is coupled to the network, allowing sufficient time for each processing element's output to propagate through the network before coupling the output of a succeeding processing element.

APPARATUS AND METHOD FOR MULTIPLE PROCESSOR SOFTWARE DEVELOPMENT include a host computer 10, a control processor 12, and a bus 16 between them and one or more nodes 14. Each node 14 includes a master processor 22 and one or more slave processors 24, all of the processors 22, 24 sharing a memory 26. Multiple processor application software may be developed using the host computer 10 and control processor 12 by concurrently monitoring every processor 22, 24 of every node 14. Each master processor 22 is monitored directly through a master transmit/receive buffer 20 between it and the bus 16, and each slave processor 24 of each node 14 is monitored indirectly through a slave transmit/receive buffer 38 in the node's shared memory 26, the buffer 38 extending between that slave processor 24 and that node's master processor 22.

A multiprocessor computer system includes fault tolerant power up logic for finding a functioning CPU to operate as logical CPU0. Each microprocessor has a physical location designation which remains constant. When the system is powered up, all of the CPUs except the CPU in physical slot 0 (CPU P0) are initially placed in an inactive sleep state. The microprocessor in physical location 0 performs its power on self test (POST), and if the CPU functions properly, the CPU is designated as logical CPU0 (CPU L0). The microprocessor then awakens the remaining CPUs and boots up the rest of the computer system. If CPU P0 is not functioning properly, after a given time period the system awakens the processor in the next physical location and repeats the process of testing the CPU. The process repeats until an operating microprocessor is found to perform the CPU L0 functions.

A multi-processor system including a main storage for storing instructions and data, a master processor for supplying to a slave processor data required for the processing to be executed by the slave processor and commanding initiation of the processing, the master processor further operating to test the operation state of the slave processor and perform processing by utilizing the result of the processing executed by the slave processor. The slave processor initiates the processing under the command of the master processor and operates to inform of the master processor of completion of the processing. The slave processor operates to execute a pause instruction for suspending temporarily activation of processing for a succeeding instruction and setting a pause indication at an indicator of the slave processor. When the pause indication is set in the slave processor, the master processor operates to reset this indication to release the slave processor from the pause state. When the pause state indication is not set, the master processor executes a clearing instruction supplied from the main storage for suspending the function to activate the succeeding instruction. The slave processor also operates to set at the indicator an indication instruction indicating completion of execution of the succedding instruction. The master processor functions to reset the indication of completed execution of instruction set at the slave processor and otherwise execute an indication resetting instruction for suspending activation of a succeeding instruction.

A programmable unit is described having one or more program running units for running a program, with at least one of the program running units having an associated stopping device by which it is possible to stop the running of the program by the program running unit with which that stopping device is associated. The described programmable unit is distinguished in that the stopping device can also cause other components of the programmable unit to be stopped, in addition to the program running unit with which it is associated.