Electronic circuitry for generation of graphics images on a computer display screen is disclosed which allows graphics capability to be added or retrofitted to computers having standard video display character generation circuitry. The graphics circuitry receives address, data and control signals from the normal computer peripheral bus. Address signals received by the graphics circuitry are interpreted as command signals and, in accordance with the command signals, data present on the computer peripheral data bus is interpreted either as graphics data to be written in a random access graphics memory or as an address location for such data in the memory. The graphics circuitry normally operates asynchronously with respect to the computer under control of the character clock generated by the character generation circuitry. Proper synchronization with computer operation is achieved by using wait commands which cause the computer circuitry to cease processing temporarily while write or read operations are being processed by the graphics circuitry. In addition, special circuitry is provided which allows the graphics circuitry to automatically increment and decrement address information stored within the circuitry.
A multifunction access circuit for use with first and second digital computers each having an address bus for supplying addresses and a data bus for supplying data. The access circuit has an address decoder with inputs for the address bus from the first computer, and an address translator circuit having address inputs for addresses supplied by the address bus of the first computer and outputs for translated addresses to the address bus of the second computer. The address translator circuit also has registers selectable by the address decoder and data inputs to program the registers so selected with data from the data bus from the first computer. Also in the access circuit is a port circuit with registers controlled by the address decoder for entry of address information from the data bus of the first computer and assertion of the address information on the address bus of the second computer. Further, a mode control circuit is connected to the address decoder and connected to the data bus to program the mode control circuit to selectively establish operation of the address translator circuit and of the port circuit. Other access circuits, devices, systems and methods are also described.
A memory access system for use with a graphics processor having an address bus, a data bus and a set of control lines. An address translator circuit connected to the address bus of the graphics processor supplies a translated address to a memory upon receipt of an address from the graphics processor. A logic circuit responds to a write signal to automatically increment the translated address and responds to a control signal to return to the translated address. Control circuitry connected to the logic circuit responds to a read signal to supply the control signal to the logic circuit.
A system for visualization on a video screen (6) in a graphical mode in which the visual information to be displayed is defined on the screen by a point by point sweeping, from page memory containing, at a given time, all of the video information to be displayed, and a video display processor (4), connected to a random access memory containing said page memory and to a display control unit (37) adapted to convert the information relative to the image composed from the contents of the memory (5) to screen (6) control signals, characterized in that central processing unit (1) is connected to the video display processor (4) by means of a single bus (12) over which are transmitted, on a time shared basis, the address fields and the data fields (15) and in that it includes in addition a control and interpretation circuit (27) capable, in response to an assignment signal generated by said central processing unit, to interpret the address field as an address field per se or as a control field for the video display processor.
A dynamic random access memory arrangement for storing digital television signal data under control of a system clock signal CK and input address signals A0 to A17 associated with the data, has a dynamic random access memory having a data input and a data output for the data, and an address input for the input address signals, the dynamic random access memory being controlled by a write enable signal WE, a row address strobe signal RAS and a column address strobe signal CAS, and a logic circuit is provided to derive the signals WE, RAS and CAS from the system clock signal CK with respective timings each determined by a leading edge of a pulse of the system clock signal CK and delay devices.
An apparatus for interfacing externally generated display data with a display terminal so that the externally generated data can be displayed on the display terminal, the apparatus including means for storing the externally generated display data, means responsive to the display control signals of the display terminal for generating addresses for accessing the storage means, wherein the access addresses are in synchronism with the display control signals, and means for logically combining the internally generated display data and the synchronized externally generated display data.
