A self-checking timer usable with a host system includes a clock and a plurality of interconnected counters. During a power-up phase the timer generates a system reset signal and counts the counters in a predetermined sequence. A flip-flop is set and reset during the power-up phase and inhibits generation of the system reset signal. During a normal operating phase, the timer generates a test signal that must be responded to by the host system to continuously inhibit generation of the system reset signal.

Microcomputers or microprocessors are required to be reset after supply of a power source voltage to the microcomputers or microprocessors is interrupted due to the replacement of the microcomputers. A time constant circuit generates a reset signal from a capacitor of the time constant circuit after a predetermined time has passed since the source voltage was applied to the microcomputers. A discharging circuit is connected to the time constant circuit, and rapidly discharges the charge stored in the capacitor of the time constant circuit after the supply of the source voltage is interrupted.

A combination watchdog timer and input voltage level detector circuit is coupled to a microcomputer (or microprocessor) for insuring proper operation thereof under various conditions. The watchdog timer is coupled to the microcomputer and is responsive to a status signal output by the microcomputer indicating the operating state thereof. Failure of the watchdog circuit to detect the status signal indicates that the microcomputer has become unstable or is in a locked up condition and causes the watchdog circuit to initiate a microcomputer reset by means of a reset trigger circuit. A voltage level detector is coupled to the input voltage source and to the reset trigger circuit for similarly initiating the resetting of the microcomputer in the event the input voltage to the microcomputer drops below a predetermined value. When power is initially applied, a power up detector coupled between the voltage level detector and the watchdog timer ensures that the reset trigger circuit maintains the microcomputer in a reset condition until the input voltage reaches a predetermined level to permit normal microcomputer operation. The present invention thus ensures that the microcomputer is maintained or is placed in a reset condition in the event of input power transients, upon initial application of power to the microcomputer, and upon the occurrence of irregularities in microcomputer program execution.

Fault tolerant operation of a microprocessor-based control system is provided by proper execution of an operating program stored in a read only memory (ROM) by a central processing unit (CPU), or microprocessor/microcomputer, as determined by monitoring program access of a select memory location within the ROM. Failure to access the select memory location within a designated time period indicates improper CPU operation and allows a shift register to output a reset signal to automatic reset circuitry for reinitializing CPU operation. The automatic reset circuitry monitors CPU operation and continually attempts to reset the CPU until proper resetting thereof is accomplished. A visual and/or aural indication of CPU reset as well as the number of times it is reset is provided to an operator. The CPU is coupled to a host computer for indicating to the host computer that the CPU has been reset and is now ready to receive data from the host computer. The present invention is particularly adapted for use in the headend of a cable television (CATV) system for ensuring proper operation of a CPU used to control program decoders and subscriber encoders, but is not limited in its application to this environment as it has application in any microprocessor-based control system.

A watchdog circuit for improving the possibility of recovery from failures, such as those caused by static discharge or RF interference, in a data processing system. A data processing system includes a main, multi-chip processor for handling the main computational burden and a single-chip processor for handling I/O functions. Additionally, the main processor periodically sends status to the single-chip processor. If the single-chip processor does not receive status within a predetermined period it generates a reset signal to the main processor. In response to the reset signal the main processor interrogates the single-chip processor to determine if the reset was caused by a failure or a power-on condition. Because of its self contained construction the single-chip processor is less susceptible to static induced failures and will improve the recovery capabilities of the system when used to monitor the main processor.