A low impedance crossunder region is formed of a low resistivity emitter diffusion within a base region of an active device which extends beneath a portion of a metallization pattern to be crossed. The low resistivity crossunder diffusion is shorted to the base region in order to prevent transistor action between the crossunder region and the base region in contrast with other emitter diffusions within the base region which form diode junctions with the base region.
An integrated circuit comprising a plurality of gain cells interspersed with a plurality of passive and active, electrically isolated components (e.g. thin-film binarily-weighted resistors and transistors). Each gain cell comprises a differential amplifier gain stage comprising a pair of emitter-coupled transistors, the coupled emitters being connected to a current source. The collectors thereof are coupled to a pair of transistors configured as a current mirror. The emitter-coupled transistors, current source and current-mirror transistors are disposed on a first level of the integrated circuit. A first output stage comprising a common-emitter transistor and a second output stage comprising a transistor having an electrically isolated emitter are disposed on the first level. An upper level of metallization is used for selectively coupling either: the output of the differential amplifier gain stage to the first output stage, thereby configuring the gain cell as a comparator; or, additionally, the second output stage transistor between the collector of the first output stage transistor and the output of the differential amplifier, thereby providing an operational amplifier circuit configuration. With such arrangement, each gain cell has a pre-configured gain stage with predetermined electrical characteristics. The manufacturer may then configure each gain cell as either an analog comparator or an operational amplifier having well-defined electrical characteristics during the final metallization process. The gain cells and passive and active components further are selectively interconnected by second level metallization to thereby configure a desired circuit.
A device accomplishes protection against breakdown of an N+ type diffused region (6) inserted in a vertical-type semiconductor integrated power structure. Such a structure comprises N+ type substrate (1) over which there is superimposed an N- type epitaxial layer (2) in which a grounded P type insulation pocket (3) is obtained. The insulation pocket (3) contains an N type region (4) including a P type region (5) for the containment of the N+ type diffused region (6). The diffused region (6) is insulated electrically with respect to the P type containment region (5).
