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Claims  |
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What I claim is:
1. A radiation sensing system comprising:
(A) signal integration type radiation sensing means responsive to radiation
and arranged to produce an electrical output indicative of the integration
of the received radiation during a signal integration time;
(B) radiation measuring means arranged to measure radiation substantially
equivalent to the radiation which said sensing means receives, said
measuring means producing an electrical output indicative of the intensity
of the received radiation; and
(C) signal integration time control means for controlling the signal
integration time of said sensing means on the basis of the outputs of said
measuring means and said sensing means,
wherein said signal integration time control means is arranged to determine
an initial signal integration time of said sensing means on the basis of
the output of said measuring means.
2. The system according to claim 1, wherein said signal integration time
control means is arranged to select said initial signal integration time
from among a plurality of different preset signal integration times on the
basis of the output of said measuring means.
3. The system according to claim 2, wherein said signal integration time
control means is arranged to control the signal integration time of the
sensing means among said preset signal integration times on the basis of
the output of said sensing means with said initial signal integration time
determined on the basis of the output of said measuring means as the
starting point.
4. The system according to claim 1, wherein said signal integration time
control means is arranged to control the signal integration time of the
sensing means on the basis of the output of said sensing means with said
initial signal integration time determined on the basis of the output of
said measuring means as the starting point.
5. The system according to claim 1, 2, 3 or 4, wherein said signal
integration time control means includes:
means for discriminating the level of the output of said sensing means,
said discrimination means producing an output indicative of the result of
said discrimination; and
means for determining the signal integration time of said sensing means on
the basis of the outputs of said measuring means and said discrimination
means, said determination means first determining said initial signal
integration time on the basis of the output of the measuring means and
thereafter varying the signal integration time on the basis of the output
of the discrimination means with said determined initial signal
integration time as the starting point.
6. The system according to claim 5, wherein said discrimination means is
arranged to produce a logic output as said discrimination result;
and said determination means includes:
a conversion circuit for receiving and converting the output of said
measuring means into digital data;
a time indication circuit responsive to said digital data formed by said
conversion circuit and to said logic output of said discrimination means
to indicate the signal integration time of said sensing means; and
a time control circuit for controlling the signal integration time of the
sensing means in accordance with an indication output of said indication
circuit.
7. The system according to claim 6, wherein said time indication circuit
includes:
a presettable up-down counter for providing digital data indicative of the
signal integration time; and
a counter controller for controlling said counter, said controller first
presetting in the counter the digital data formed by said conversion
circuit and thereafter varying the count value of the counter on the basis
of the logic output of said discrimination means.
8. The system according to claim 7, wherein said discrimination means
includes:
a comparison circuit for comparing the level of the output of said sensing
means with a predetermined range of levels, said comparison circuit
producing said logic output as a result of said comparison.
9. The system according to claim 8, wherein said discrimination means
further includes:
a peak detection circuit for detecting a peak level of the output of said
sensing means;
said comparison circuit is arranged to compare the peak level detected by
said detection circuit with said range of levels.
10. The system according to claim 6, wherein said discrimination means
includes:
a comparison circuit for comparing the level of the output of said sensing
means with a predetermined range of levels, said comparison circuit
producing said logic output as a result of said comparison.
11. The system according to claim 10, wherein said discrimination means
further includes:
a peak detection circuit for detecting a peak level of the output of said
sensing means;
said comparison circuit is arranged to compare the peak level detected by
said detection circuit with said range of levels.
12. The system according to claim 5, wherein said discrimination means
includes:
a comparison circuit for comparing the level of the output of said sensing
means with a predetermined range of levels, said comprison circuit
producing said output as a result of said comparison.
13. The system according to claim 12, wherein said discrimination means
further includes:
a peak detection circuit for detecting a peak level of the output of said
sensing means;
said comprison circuit is arranged to compare the peak level detected by
said detection circuit with said range of levels.
14. An image scanning system comprising:
(A) image sensing means having an array of a plurality of signal
integration type sensing elements, each of which produces an electrical
signal corresponding to an integration of a received portion of an image
light during a signal integration time, said sensing means providing, as
an output thereof, the signals produced by said elements;
(B) measuring means for measuring the intensity of a light substantially
equivalent to at least a portion of said image light, said measuring means
producing an output indicative of the intensity of said light;
(C) indication means for indicating the signal integration time of the
sensing elements in said sensing means;
(D) first control means for controlling the signal integration time of said
sensing elements in said sensing means in accordance with the time
indicated by said indication means; and
(E) second control means for controlling said indication means, said second
control means controlling to cause the indication means to first indicate
an initial integration time on the basis of the output of said measuring
means and thereafter change indication of the integration time on the
basis of the output of said sensing means.
15. The system according to claim 14, wherein said indication means is
arranged to select said initial signal integration time from among a
plurality of different preset signal integration times on the basis of the
output of said measuring means under the control of said second control
means.
16. The system according to claim 15, wherein said indication means is
arranged to change the signal integration time of said sensing means, from
one to another of said preset signal integration times, on the basis of
the output of said sensing means under the control of said second control
means.
17. The system according to claim 14, 15 or 16, wherein said indication
means includes:
means for discriminating the level of the output of said sensing means,
said discrimination means producing an output indicative of the result of
said discrimination; and
means for determining the signal integration time of said sensing means on
the basis of the outputs of said measuring means and said discrimination
means, said determination means first determining said initial signal
integration time on the basis of the output of said measuring means and
thereafter varying the signal integration time on the basis of the output
of said discrimination means under the control of said second control
means.
18. The system according to claim 17, wherein said discrimination means is
arranged to produce a logic output as said discrimination result and
wherein said determination means includes:
a conversion circuit for receiving and converting the output of said
measuring means into digital data; and
a time indication circuit responsive to said digital data formed by said
conversion circuit and to said logic output of said discrimination means
to indicate the signal integration time of said sensing means;
said first control means controlling the signal integration time of said
sensing means in accordance with an indication output of said indication
circuit.
19. The system according to claim 17, wherein said time indication circuit
includes:
a presettable up-down counter for providing digital data indicative of the
signal integration time; and
a counter controller for controlling said counter, said controller first
presetting in said counter said digital data formed by said conversion
circuit and thereafter varying the count value of said counter on the
basis of the logic output of said discrimination means.
20. The system according to claim 19, wherein said discrimination means
includes:
a comparison circuit for comparing the level of the output of said sensing
means with a predetermined range of levels, said comparison circuit
producing said logic output as a result of said comparison.
21. The system according to claim 20, wherein said discrimination means
further includes a peak detection circuit for detecting a peak level of
the output of said sensing means; and wherein said comparison circuit is
arranged to compare the peak level detected by said detection circuit with
said range of levels.
22. An image scanning system comprising:
(A) image sensing means having an array of a plurality of signal
integration type sensing elements, each of which produces and stores an
amount of an electrical signal corresponding to an integration amount of a
received portion of an image light for each image scanning, said sensing
means providing, as an output thereof, the signals produced by said
elements;
(B) measuring means for measuring the intensity of a light substantially
equivalent to at least a portion of said image light, said measuring means
producing an output indicative of the intensity of said light;
(C) first control means for controlling the amount of the electrical signal
to be produced and stored in each of said sensing elements in said sensing
means for each image scanning; and
(D) second control means for controlling said first control means, said
second control means causing the first control means to first control said
signal amount on the basis of the output of said measuring means and
thereafter control said signal amount on the basis of the output of said
sensing means.
23. The system according to claim 22, wherein said first control means
includes:
a conversion circuit for receiving and converting the output of said
measuring means into first digital data;
a comparison circuit for comparing the level of the output of said sensing
means with a predetermined range of levels, said comparison circuit
producing second digital data as a result of said comparison; and
a control circuit for controlling said signal amount to be produced and
stored in each of the sensing elements in said sensing means for each
image scanning on the basis of said first and second digital formed by
said conversion circuit and said comparison circuit;
said second control means causing said control circuit to first control the
signal amount on the basis of said first digital data and thereafter
control the signal amount on the basis of said second digital data. |
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Claims |
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Description |
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BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to an image scanning system, and more particularly
to improvements in the control of the signal integration time of image
sensing means in an image scanning system using signal integration type
image sensing means.
2. Description of the Prior Art
In recent years, a one-dimensional or two-dimensional signal integration
type image sensing means such as a charge-coupled device (CCD) has become
used in various fields. Such an image sensing means produces an output
linearly proportional to the intensity of incident light and therefore its
dynamic range is narrow. To cause the image sensing means to respond to a
variation in the intensity of a wide range of incident light, a method has
been proposed in which an upper limit reference level determined by the
saturation level of the output of the sensing means and a lower limit
reference level determined with noise such as dark current taken into
account are preset, the output level of the sensing means relative to
these reference levels is determined by level determination means and the
signal integration time of the sensing means is stepwise changed by
integration time control means so that the output level of the sensing
means is within a predetermined range of levels, thereby enlarging the
dynamic range.
Heretofore, design has been made such that the controllable longest
integration time or the controllable shortest integration time or the
medium integration time is preselected as an initial integration time set
by the integration time control means. However, if this has been done, for
example, in a system wherein the controllable shortest integration time is
set as the initial integration time, where the intensity of the light
incident on the sensing means is low, a considerable time has been
required until an output of appropriate level is obtained from the sensing
means by successively changing the integration time to prolong it by the
cooperation of level determination means and integration time control
means. Conversely, in a system wherein the controllable longest
integration time is set as the initial integration time, a similar demerit
has occurred where the intensity of the incident light is high. On the
other hand, in a system wherein a medium suitable integration time is set
as the initial integration time, such inconvenience is alleviated to some
extent, but where a variation in intensity of light over a very wide range
is the object, such system is still insufficient and a similar demerit has
occurred when the intensity of the incident light has been very high or
very low.
SUMMARY OF THE INVENTION
The present invention has been made in view of such inconveniences peculiar
to the prior art and has as its primary object the provision of a novel
integration time control method which, as a method of controlling the
signal integration time of signal integration type image sensing means in
an image scanning system using such sensing means, can clear off the
inconveniences peculiar to the prior art regarding the control of the
signal integration time of the sensing means.
It is another object of the present invention to provide improvements in an
image scanning system using signal integration type image sensing means
and adapted to stepwise control the signal integration time of the sensing
means (i.e., the amount of the electrical signal to be produced and stored
for each image scanning) on the basis of the output level thereof, whereby
the time required for the setting of an integration time corresponding to
the intensity of incident light can be greatly shortened and accordingly,
for a certain intensity of incident light, an output of appropriate level
can be obtained from the sensing means in a very short time.
To achieve such objects, according to the present invention, there is
provided a radiation sensing system or an image scanning system having the
following characteristic construction. The system includes: signal
integration type radiation sensing means producing an electrical output
capable of indicating the distribution pattern of incident radiation;
means for measuring radiation substantially equivalent to the radiation
incident on the sensing means and producing an electrical output capable
of indicating the intensity thereof; and means for controlling the signal
integration time of the sensing means on the basis of the output of the
measuring means and the output of the sensing means.
In a preferred embodiment of the present invention, the integration time
control means is designed to determine the initial integration time on the
basis of the output of the measuring means, and thereafter stepwise
control the integration time on the basis of the output of the sensing
means with the initial integration time as the starting point.
Also, in one embodiment, the integration time control means is designed to
use the peak level of the output of the sensing means as the basis of the
determination as disclosed, for example, in U.S. Pat. Nos. 4,305,657
entitled "Range Finding Device", 4,283,137 entitled "Image Scanning
System" and 4,329,033 entitled "Distance Detecting Device and Focus
Control System Utilizing the Same" all of which were assigned to the same
assignee of the subject application, in controlling the integration time
among a plurality of preset different integration times on the basis of
the output of the sensing means, but may also use the average level of the
output as the basis of the determination or, as disclosed, for example, in
U.S. Pat. No. 4,004,852, may use as the basis of the determination data
obtained by quantizing the output of the sensing means.
Thus, according to the present invention, the intended purposes are
completely achieved and there is provided a radiation sensing system or an
image scanning system which is very excellent in responsiveness, that is,
which can obtain the output of proper level pf the sensing means in a
short time.
Other objects and features of the present invention will become apparent
from the following detailed description of an embodiment thereof taken in
conjunction with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a model view for illustrating a method of controlling the signal
integration time of signal integration type image sensing means which is
the base of the present invention.
FIG. 2 is a model view showing an embodiment in which the image scanning
system according to the present invention is applied to the focus
detecting device of a single lens reflex camera.
FIG. 3 is a circuit diagram showing the construction of the electric
circuitry of the camera shown in FIG. 2, displayed in halves in FIG. 3A
and FIG. 3B.
FIG. 4 is a timing chart showing the relation between the output of a 3-bit
up-down counter shown in FIG. 3 and the signal integration time.
FIG. 5 is a timing chart showing various control signals produced by a
timing control circuit shown in FIG. 3.
DESCRIPTION OF THE PREFERRED EMBODIMENT
Reference is first had to FIG. 1 to describe the method of controlling the
signal integration time of image sensing means which is the basis of the
present invention. In FIG. 1, V.sub.MAX and V.sub.MIN are upper and lower
limit reference levels between which the sensing means operates linearly.
This figure shows the manner in which the accumulating time is changed
between t.sub.1 and t.sub.8 so that the output level of the sensing means
lies between the upper limit and lower limit reference levels.
Reference is now had to FIG. 2 and so on to describe an embodiment in which
the image scanning system according to the present invention is applied to
the focus detecting device of a single lens reflex camera. In FIG. 2, LS
designates a picture-taking lens, FP denotes a film, QM designates a quick
return mirror having a light-transmitting portion LP in the center
thereof, and SM denotes an auxiliary mirror for downwardly reflecting the
transmitted light from the light-transmitting portion LP of the mirror QM.
The light beam reflected by the auxiliary mirror SM enters a prism PM,
where it is divided into three light beams which respectively enter the
three image scanning sections SD.sub.1, SD.sub.2 and SD.sub.3 of the image
sensing means SD. These three image scanning sections SD.sub.3, SD.sub.1
and SD.sub.2 are adapted to receive the incident lights respectively at a
position optically equivalent to the surface the film FP, a position
slightly forward of the equivalent position and a position slightly
rearward of the equivalent position due to the action of the prism PM.
Each of the image scanning sections SD.sub.1, SD.sub.2 and SD.sub.3 has a
one-dimensional array of a plurality of signal integration type
light-receiving elements as will later be described. FS designates a
focusing screen, CL denotes a condenser lens, PN designates a penta prism,
EL denotes an eyepiece lens, and ML designates a metering condenser lens
which condenses light on a metering photoelectric conversion element PE.
MT designates a display meter. As conceptionally shown in broken line in
FIG. 2, the initial setting of the signal integration time of the image
sensing means SD may be effected by the output of the metering
photoelectric conversion element PE.
Referring to FIG. 3, SD.sub.3 is the middle image scanning section of the
image sensing means SD disposed so as to receive light at a position
optically equivalent to the surface of the film FP and, in the present
embodiment, the signal integration time of the image sensing means SD is
controlled on the basis of the output of the image scanning section
SD.sub.3. S.sub.1 -S.sub.n designate light receiving elements (arranged
one-dimensionally) included in the image scanning section SD.sub.3, and
D.sub.1 and D.sub.2 denote dummy elements masked, for example, by a mask
MS(which can be formed by evaporation of Al) for dark current detection.
FA.sub.1, FA.sub.2, . . . , FA.sub.m (m=n+2) designate integration clear
gates responsive to the high of an integration clear signal ICG to clear
the charges stored in the light-receiving elements S.sub.1 -S.sub.n and
dummy elements D.sub.1, D.sub.2. FB.sub.1, FB.sub.2, . . . , FB.sub.m
denote charge shift gates responsive to the high of a shift pulse SH to
shift to charge transfer analog shift registers CA.sub.1 -CA.sub.2m the
charges stored in the light-receiving elements S.sub.1 -S.sub.n
corresponding to the integrated amount of the light incident thereon and
the charges corresponding to the dark currents stored in the dummy
elements D.sub.1 and D.sub.2. The analog shift registers CA.sub.1
-CA.sub.2m are of the two-phase driven type operated by clock pulses
.0..sub.1 and .0..sub.2, and the transferred charges thereof are put out
as voltage information at the last stage through a charge-voltage
converting circuit comprising resistors R.sub.1, R.sub.2, R.sub.3 and FET
FC.sub.1, FC.sub.2.
AG.sub.1 designates an analog gate for taking out only the signals obtained
by the dummy elements D.sub.1 and D.sub.2, of the output of the image
scanning section SD.sub.3, and a holding capacitor C.sub.1, a resistor
R.sub.4 and a buffer amplifier BP subsequent to the analog gate AG.sub.1
together constitute a dark current signal holding circuit. The resistor
R.sub.4 is a resistor for forming a low-pass filter together with the
capacitor C.sub.1, and is not always necessary. Resistors R.sub.5,
R.sub.6, R.sub.7, R.sub.8 and an operational amplifier OP.sub.1 together
constitute a differential amplifier circuit as a dark current compensating
differential circuit, and this circuit puts out a dark-current-compensated
true scanning output VF by subtracting the dark current signal components
obtained by the dummy elements D.sub.1 and D.sub.2 which are held by the
dark current signal holding circuit from the scanning output including the
dark current components obtained by the light-receiving elements S.sub.1
-S.sub.n.
AG.sub.2 designates an analog gate for taking out only the signals
corresponding to the light-receiving elements S.sub.1 -S.sub.n, of the
output of the differential amplifier circuit. PD denotes a peak detecting
circuit (which may also detect the average value) for detecting, for
example, the peak value (hereinafter referred to as VP) of the signal
obtained through the analog gate AG.sub.2. PH designates a peak holding
circuit for holding the peak value VP detected by the peak detecting
circuit. R.sub.9, R.sub.10 and R.sub.11 denote voltage dividing resistors
for obtaining the voltages V.sub.MAX and V.sub.MIN corresponding to the
upper limit and lower limit reference levels described in connection with
FIG. 1. CP.sub.1 designates a comparator which compares the held value VP
of the peak holding circuit PH with the upper limit reference voltage
V.sub.MAX and puts out a high level signal when VP>V.sub.MAX and puts out
a low level signal when VP.ltoreq.V.sub.MAX. CP.sub.2 denotes a comparator
which compares the held value VP with the lower limit reference voltage
V.sub.MIN and puts out a high level signal when VP<V.sub.MIN and puts out
a low level signal when VP.gtoreq.V.sub.MIN. IV.sub.1 designates an
inverter for inverting the output of the comparator CP.sub.1. The output
of the inverter IV.sub.1 is imparted to an up-down counter UDC(which is a
binary up-down counter of 3-bit construction) as a signal for controlling
the counting mode of this up-down counter UDC. The up-down counter UDC is
set so as to assume an up count mode by the high of the output of the
inverter IV.sub.1 and to assume a down count mode by the low of the output
of the inverter IV.sub.1. OR.sub.1 denotes an OR gate for taking the
logical sum of the output of the comparator CP.sub.1 and the output of the
comparator CP.sub.2. EX denotes an exclusive OR gate for taking the
exclusive-or of the 3-bit outputs Q.sub.1, Q.sub.2, Q.sub.3 of the up-down
counter UDC and the output of the inverter IV.sub.1. AN.sub.1 designates
an AND gate for taking the logical multiple of the output of the OR gate
OR.sub.1, the output of the exclusive OR gate EX and the counting pulse CP
from a timing control circuit TCC to be described. The output of the AND
gate AN.sub.1 is imparted to the up-down counter UDC as the count clock of
this up-down counter UDC. The exclusive OR gate EX is for preventing the
resetting of the up-down counter UDC when the integration time has been
set to the shortest time t.sub.1 or the longest time t.sub.8 and further
the shift information toward the short time or the long time side has been
put out from the comparator CP.sub.1 or CP.sub.2 and for fixing the
integration time to the currently set shortest or longest integration
time. The relations between the 3-bit outputs Q.sub.1 -Q.sub.3 of the
up-down counter UDC and the eight stages of integration time t.sub.1
-t.sub.8 designated thereby are as shown in FIG. 4.
TCC designates a timing control circuit for generating various control
pulses and control signals in accordance with the timing chart shown in
FIG. 5. CP is the counting pulse of the up-down counter UDC generated once
each time the signals of the image scanning sections SD.sub.1 -SD.sub.3
are read out (that is, the integration time controlling pulse). A.0..sub.1
is a gate controlling signal for the analog gate AG.sub.1 for taking out
through the analog gate AG.sub.1 the signals of the portions necessary for
detection of dark current during each read-out, namely, the signals
corresponding to the dummy elements D.sub.1 and D.sub.2. A.0..sub.2 is a
gate controlling signal for the analog gate AG.sub.2 for taking out
through the analog gate AG.sub.1 the signals corresponding to the
light-receiving elements S.sub.1 -S.sub.n, of the output of the
differential amplifier circuit OP.sub.1, during each read-out. .0..sub.R
is a peak resetting control signal for resetting the peak detecting
circuit PD, for example, immediately after each read-out is initiated.
.0..sub.H is a peak holding control signal for causing the peak detection
value VP before the peak detecting circuit PD is reset to be held by the
peak holding circuit PH each time each read-out is terminated. SH is a
gate controlling pulse (shift pulse) for the charge shift gates FB.sub.1
-FB.sub.m in the image scanning section SD.sub.3. ICG is a gate
controlling signal (integration clear signal) for the integration clear
gates FA.sub.1 -FA.sub.m. .0..sub.1 and .0..sub.2 are transfer clock
pulses for the charge transfer analog shift registers CA.sub.1 -CA.sub.2m
(that is, the analog shift registers CA.sub.1 -CA.sub.2m are of the
two-phase driven type, and the shift pulse SH is synchronous with
.0..sub.1). RS is a reset pulse for the charge-voltage converting circuit
FET FC.sub.1. The above-described signals 2CG, SH, .0..sub.1, .0..sub.2
and RS are also supplied to the other image scanning sections SD.sub.1 and
SD.sub.2.
The timing control circuit TCC has the function of controlling the signal
integration time (charge accumulating time) of the image scanning sections
SD.sub.1 -SD.sub.3 on the basis of the time information designated by the
outputs Q.sub.1 -Q.sub.3 of the up-down counter UDC, and specifically
realizes the control of the integration time by controlling the period of
time from the falling of the integration clear signal ICG to its low level
indicated by t in FIG. 5 till the rising of the shift pulse SH between the
eight stages t.sub.1 -t.sub.8 in accordance with the conditions of the
outputs Q.sub.1-Q.sub.3 of the up-down counter UDC. Thus, the actual
integration time of the image scanning sections SD.sub.1 -SD.sub.3 is "the
image t+ the duration .DELTA.t of the high level of the shift pulse SH".
Incidentally, the image scanning sections SD.sub.1 -SD.sub.3 is of the
two-phase driven type as previously described, but the signal of each
element thereof is put out in synchronism with .0..sub.1 and the
outputting thereof is initiated in synchronism with the shift pulse SH.
Now, in accordance with the improvement of the present invention, a
construction for initial setting of the integration time as will
hereinafter be described is added to the above-described construction of
the image scanning system. In FIG. 3, a metering photoelectric conversion
element PE is connected between the input terminals of a high input
impedance operational amplifier MP.sub.1. LD.sub.1 designates a
logarithmic compression element for logarithmically compressing the
photocurrent produced in the photoelectric conversion element PE
correspondingly to the brightness of the object to be photographed, and
CS.sub.1 denotes a constant current source which, together with a resistor
R.sub.20, supplies a bias voltage to the non-inverting input terminal of
the operational amplifier MP.sub.1. R.sub.21 -R.sub.23 designate
operational resistors, OP.sub.5 denotes an operational amplifier, CP.sub.5
designates a comparator, and Mg.sub.1 denotes an aperture controlling
magnet. VR.sub.1 designates a variable resistor in which information "Sv -
Tv", i.e., the film speed information Sv minus the shutter time
information Tv, and in the operational amplifier OP.sub.5, this
information and the object luminance information which is the output of
the operational amplifier MP.sub.1 are computed and aperture information
is put out to the output of the operational amplifier OP.sub.5. The
aperture information is displayed by an aperture information displaying
ammeter MT and ah aperture corresponding to the luminance of the object to
be photographed is automatically set through a variable resistor VR.sub.2
operatively associated with an aperture adjusting member, the comparator
CP.sub.5 and the magnet Mg.sub.1. Vc applied to the non-inverting inputs
H) of the operational amplifier OP.sub.5 and the comparator CP.sub.5 is a
bias level setting reference voltage.
On the other hand, VR.sub.3 designates a variable resistor operatively
associated with a shutter time setting member. The variable resistor
VR.sub.3, together with a capacitor C.sub.5, constitutes a timer circuit.
SW.sub.10 denotes a count switch adapted to be opened substantially
simultaneously with the start of movement of the first curtain of the
shutter ST (FIG. 2). When the voltage across the capacitor C.sub.5 reaches
a predetermined value, a Schmidt trigger circuit ST is inverted to
deenergize a magnet Mg.sub.2 for controlling the second curtain of the
shutter ST, thus terminating the exposure. SW.sub.1 denotes a main switch,
and E designates a power source. ADC denotes an A/D converter for
converting the output of the operational amplifier MP.sub.1, for example,
into a 3-bit digital data. OS designates a one-shot circuit. AN.sub.2
denotes an AND gate for taking the logical multiply of the output pulse of
the one-shot circuit OS and the A/D conversion termination pulse from the
terminal ED of the A/D converter ADC. The output of the AND gate AN.sub.2
is imparted to the preset enable terminal PE of the up-down counter UDC.
Now, in the above-described construction, when the main switch SW.sub.1 of
the camera is closed at time T.sub.1 (see FIG. 5), the exposure amount
control circuit of the camera starts operating and the one-shot circuit OS
generates a pulse which assumes high level during the time from time
T.sub.1 till time T.sub.3. Also, the A/D converter ADC starts the A/D
conversion of the output of the operational amplifier MP.sub.1 which is
the information corresponding to the luminance of the object to be
photographed. When the A/D converter ADC terminates the A/D conversion of
the object luminance information at time T.sub.2, an A/D conversion
termination pulse is generated from the terminal ED thereof and
accordingly, by the output of the AND gate AN.sub.2, the preset enable
terminal PE of the integration time setting up-down counter UDC assumes
high level, whereby the output of the A/D converter ADC is preset to the
up-down counter UDC. For example, if the conditions of the output
terminals Q.sub.1, Q.sub.2 and Q.sub.3 of the A/D converter ADC are high
level, low level and high level, respectively, the output terminals
Q.sub.1, Q.sub.2 and Q.sub.3 of the up-down counter UDC also assume
similar conditions and accordingly, the first integration time becomes
t.sub.6 (see FIG. 4).
On the other hand, upon closing of the main switch SW.sub.1, the timing
control circuit TCC starts to put out transferring clock pulses .0..sub.1,
.0..sub.2 and reset pulse RS to the image scanning sections SD.sub.1
-SD.sub.3 at time t.sub.1 and renders the integration clear signal ICG
high and opens the integration clearing gates FA.sub.1 -FA.sub.m, thereby
inhibiting the accumulation of the produced charges in the dummy elements
D.sub.1, D.sub.2 and the light-receiving elements S.sub.1 -S.sub.n.
Thereafter, at time T.sub.3, the output of the one-shot circuit OS is
inverted to low level, whereupon in response to this signal, the
integration clear signal ICG is rendered low as shown in FIG. 5 and the
integration clearing gates FA.sub.1 -FA.sub.m are closed, whereby the
accumulation of the produced charges in the elements D.sub.1, D.sub.2 and
S.sub.1 -S.sub.n is initiated while, at the same time, the accumulating
time designated by the outputs Q.sub.1 -Q.sub.3 of the up-down counter UDC
(in this case, the accumulating time is t.sub.6) begins to be counted and,
when this time counting is terminated, the shift pulse SH is put out.
Accordingly, at this point of time, the charge shifting gates FB.sub.1
-FB.sub.m are opened, whereby the charges accumulated in the elements
D.sub.1, D.sub.2 and SD.sub.1 -SD.sub.n while said time counting is being
effected are introduced through the charge shifting gates FB.sub.1
-FB.sub.m into the corresponding bits of the charge transferring analog
shift resisters CA.sub.1 -CA.sub. 2m, whereafter the charges are
transferred through the analog shift resisters CA.sub.1 -CA.sub.2m to the
charge-voltage converting circuit, where the charges are converted into a
voltage and put out as voltage information. The timing control circuit
TCC, after having put out the shift pulse SH, again renders the
integration clear signal ICG high and opens the integration clearing gates
FA.sub.1 -FA.sub.m, thereby inhibiting the accumulation of the produced
charges in the elements D.sub.1, D.sub.2 and S.sub.1 -S.sub.n. Now, when
the outputting of scanning signals from the image scanning sections
SD.sub.1 -SD.sub.3 is thus initiated, the timing control circuit TCC
renders the gate controlling signal A.0..sub.1 to the analog gate AG.sub.1
high at a timing whereat the signal corresponding to the dummy elements
D.sub.1 and D.sub.2 is put out as shown in FIG. 5, and opens the analog
gate AG.sub.1 and thus, the signal corresponding to the dummy elements
D.sub.1 and D.sub.2 is held as the dark current signal of the image
scanning section SD.sub.3 by the capacitor C.sub.1, and the dark current
signal thus held is imparted to one input of the differential amplifier
circuit through the buffer amplifier BP. Thus, the differential amplifier
circuit then receives at the other input thereof the signal corresponding
to the light-receiving elements S.sub.1 -S.sub.n, whereby it puts out said
signal minus the dark current signal component, namely, the
dark-current-compensated scanning signal VF. On the other hand, at this
time, the timing control circuit renders the gate controlling signal
A.0..sub.2 to the analog gate AG.sub.2 high during the period of time in
which the signal corresponding to the light-receiving elements S.sub.1
-S.sub.n is put out from the image scanning section SD.sub.3 as shown in
FIG. 5, thereby opening the analog gate AG.sub.2 and accordingly, of the
output of the differential amplifier circuit, the output corresponding to
the light-receiving elements S.sub.1 -S.sub.n is imparted to the peak
detecting circuit PD. The peak detecting circuit PD is already reset by
the reset signal .0..sub.R from the timing control circuit TCC as shown in
FIG. 5 during the period of time in which, for example, the signal
corresponding to the dummy elements D.sub.1 and D.sub.2, and is imparted
the output of the differential amplifier circuit corresponding to the
light-receiving elements S.sub.1 -S.sub.n through the analog gate
AG.sub.2, whereby it detects the peak value thereof. When the outputting
of the signal corresponding to the light-receiving elements S.sub.1
-S.sub.n from the image scanning section SD.sub.3 is terminated, the
timing control circuit TCC renders the gate controlling signal A.0..sub.2
low as shown in FIG. 5 and closes the analog gate AG.sub.2 to thereby
terminate the peak value detection by the peak detecting circuit PD,
whereafter it imparts a hold signal .0..sub.H to the peak holding circuit
PH to cause the same to hold the peak detection output VP of the peak
detecting circuit PD at this point of time. When the peak value VP is held
by the peak holding circuit PH, the comparators CP.sub.1 and CP.sub.2
compare the held peak value VP with the upper limit and lower limit
reference voltages V.sub.MAX and V.sub.MIN, and put out the result of the
comparison as a high or low logic signal. Generally, good control of the
integration time of the image sensing device disposed within the camera
can be accomplished by the output of the metering photoelectric conversion
element | | |
