 |
Claims  |
|
|
What is claimed is:
1. A memory nonlinear noise-blanking circuit responsive to a composite
signal including an information signal distorted by a noise signal, said
memory nonlinear noise blanking circuit comprising:
delay means responsive to the composite signal for producing a delayed
signal;
means for producing a first reference signal;
threshold detector means including:
first comparator means having an inverting input terminal responsive to the
first reference signal and a non-inverting input terminal responsive to
the composite signal, for producing a first comparison signal;
inverter means responsive to the composite signal for producing an inverted
signal;
second comparator means having an inverting input terminal responsive to
the first reference signal and a non-inverting input terminal responsive
to the inverted signal, for producing a second comparison signal;
and first gate means having a first input terminal responsive to said first
comparison signal and a second input terminal responsive to said second
comparison signal, for producing a threshold signal at an output terminal
thereof, said threshold signal rendered in a first state in response to
one set of conditions of said first and second comparison signals and in a
second state in response to another set of conditions of said first and
second comparison signals;
timer means responsive to said threshold signal for producing a timing
signal, wherein said timing signal is in a first state when said threshold
signal is in said first state, and wherein said timing signal changes to a
second state a predetermined time after said threshold signal changes to
said second state;
signal generator means for producing an approximation signal selected to
approximate the value of the information signal while said timer means is
in said first state;
and second gate means responsive to said delayed, timing, and approximation
signals for producing an output signal at an output terminal thereof,
wherein said output signal represents said approximation signal when said
timing signal is in said first state, and represents said delayed signal
when said timing signal is in said second state.
2. The memory nonlinear noise-blanking circuit of claim 1 wherein the
information signal is a digital signal.
3. The memory nonlinear noise-blanking circuit of claim 1 wherein the
information signal is an analog signal.
4. The memory nonlinear noise-blanking circuit of claim 1 wherein the delay
means is an analog delay line having a delay time of .DELTA.t.sub.1, and
wherein .DELTA.t.sub.1 is a longer than the duration of the noise signal.
5. The memory nonlinear noise-blanking circuit of claim 4 wherein the
analog delay line includes a charge-coupled device.
6. The memory nonlinear noise-blanking circuit of claim 1 wherein the
magnitude of the first reference signal is greater than the magnitude of
the information signal, and wherein the magnitude of the first reference
signal is exceeded by the composite signal.
7. The memory nonlinear noise-blanking circuit of claim 1 wherein the
predetermined time is equal to .DELTA.t.sub.1 plus the rise time of the
noise signal.
8. The memory nonlinear noise-blanking circuit of claim 1 including:
sign-detector means responsive to the delayed signal for producing a
flip-flop signal having a first state when the delayed signal is positive
and having a second state when the delayed signal is negative;
negative dc voltage generator means for producing a negative dc signal,
wherein the signal generator means is responsive to said negative dc
signal;
positive dc voltage generator means for producing a positive dc signal,
wherein the signal generator means is responsive to said positive dc
signal;
and wherein the approximation signal comprises said positive dc signal when
said flip-flop signal is in said first state and wherein the approximation
signal comprises said negative dc signal when said flip-flop signal is in
said second state.
9. The memory nonlinear noiseblanking circuit of claim 8 wherein the sign
detector means includes
means for producing a second reference signal;
comparator means having an inverting input terminal responsive to said
second reference signal and a non-inverting input terminal responsive to
the delayed signal, for producing a comparison signal, said comparison
signal having a first state when the delayed signal exceeds said second
reference signal and having a second state when said second reference
signal exceeds said delayed signal;
and D-type flip-flop means having a D-input terminal responsive to said
comparison signal and a clock input terminal responsive to the threshold
signal, for producing the flip-flop signal, wherein the flip-flop signal
is triggered to the first state when the threshold signal and said
comparison signal are in the first state, and wherein said flip-flop
signal is triggered to the second state when the threshold signal is in
the first state and said comparison signal is in the second state, wherein
the signal generator means is responsive to said flip-flop signal.
10. The memory nonlinear noise-blanking circuit of claim 1 including:
means for producing a second reference signal;
comparator means having an inverting input terminal responsive to said
second reference signal and a non-inverting input terminal responsive to
the delayed signal, for producing a comparison signal, said comparison
signal having a first state when the delayed signal exceeds said second
reference signal and having a second state when said second reference
signal exceeds said delayed signal;
D-type flip-flop means having a D input terminal responsive to said
comparison signal and a clock input terminal responsive to the threshold
signal, for producing a flip-flop signal, said flip-flop signal triggered
to a first state when the threshold signal and said comparison signal are
in the first state, and said flip-flop signal triggered to a second state
when the threshold signal is in the first state and said comparison signal
is in said second state;
wherein the signal generator means includes a negative dc voltage generator
means for producing a negative dc signal, and a positive dc voltage
generator means for producing a positive dc signal;
and wherein the gate means includes a three-channel analog multiplexer
having a first control terminal responsive to said flip-flop signal, a
second control terminal responsive to the timing signal, a first data
input terminal responsive to the delayed signal, a second data input
terminal responsive to said negative dc signal, and a third data input
terminal responsive to said positive dc signal, for producing the output
signal, wherein the output signal comprises the delayed signal when said
flip-flop signal is in the second state and the timing signal is in the
second state, and wherein the output signal comprises the delayed signal
when said flip-flop signal is in the first state and the timing signal is
in the second state, and wherein the output signal comprises said negative
dc signal when said flip-flop signal is in the second state and the timing
signal is in the first state, and wherein the output signal comprises said
positive dc signal when said flip-flop signal is in the first state and
the timing signal is in the first state.
11. A memory nonlinear noise-blanking circuit responsive to a composite
signal including an information signal distorted by a noise signal, said
memory nonlinear noise-blanking circuit comprising:
delay means responsive to the composite signal for producing a delayed
signal;
means for producing a first reference signal;
threshold detector means including:
first comparator means having an inverting input terminal responsive to the
first reference signal and a non-inverting input terminal responsive to
the composite signal, for producing a first comparison signal;
first inverter means responsive to the composite signal for producing a
first inverted signal;
second comparator means having an inverting input terminal responsive to
the first reference signal and a non-inverting input terminal responsive
to the inverted signal, for producing a second comparison signal;
and first OR gate means responsive to said first and said second comparison
signals, for producing a threshold signal at an output terminal thereof,
said threshold signal rendered in a first state in response to one set of
conditions of said first and second comparison signals and in a second
state in response to another set of conditions of said first and second
comparison signals;
first timer means responsive to said threshold signal for producing a first
timing signal, wherein said first timing signal is in a first state when
said threshold signal is in said first state, and wherein said first
timing signal changes to a second state a first predetermined time after
said threshold signal changes to said second state;
and sample and hold means having a data input terminal responsive to said
delayed signal and a control input terminal responsive to said first
timing signal, for producing a sampled signal at an output terminal
thereof, wherein while said timing signal is in said first state said
sampled signal is held constant at a value representing the value of said
delayed signal when said timing signal changed to said first state, and
wherein while said timing signal is in said second state said sampled
signal is representative of said delayed signal.
12. The memory nonlinear noise-blanking circuit of claim 11 wherein the
information signal is a digital signal.
13. The memory nonlinear noise-blanking circuit of claim 11 wherein the
information signal is an analog signal.
14. The memory nonlinear noise-blanking circuit of claim 11 wherein the
delay means is an analog delay line having a delay time of .DELTA.t.sub.1,
and wherein .DELTA.t.sub.1 is longer than the duration of the noise
signal.
15. The memory nonlinear noise-blanking circuit of claim 11 wherein the
analog delay line includes a charge-coupled device.
16. The memory nonlinear noise-blanking circuit of claim 11 wherein the
magnitude of the first reference signal is greater than the magnitude of
the information signal, and wherein the magnitude of the first reference
signal is exceeded by the composite signal.
17. The memory nonlinear noise-blanking circuit of claim 11 wherein the
threshold detector means includes:
means for producing a derivative reference signal;
derivative threshold means for producing a derivative threshold signal
having a first state when the composite signal exceeds the derivative
reference signal and having a second state when the composite signal does
not exceed the derivative reference signal;
second timer means responsive to said derivative threshold signal for
producing a second timing signal, wherein said second timing signal
changes to a first state a second predetermined time after said derivative
threshold signal changes to said first state, and wherein said second
timing signal changes to a second state a third predetermined time after
said derivative threshold signal changes to said second state;
and second OR gate means disposed between the first timer means and the
sample and hold means such that said second OR gate means is responsive to
the first timing signal at a first input terminal thereof and is
responsive to said second timing signal at a second input terminal
thereof, for producing an output signal, and wherein the sample and hold
means is responsive to said sixth output signal at the control terminal
thereof.
18. The nonlinear noise-blanking circuit of claim 17 wherein the derivative
threshold means includes:
differentiator means responsive to the composite signal for producing a
first derivative signal;
third comparator means having an inverting input terminal responsive to the
derivative reference signal and a non-inverting input terminal responsive
to said first derivative signal, for producing a third comparison signal;
second inverter means responsive to said first derivative signal for
producing an inverted signal;
fourth comparator means having an inverting input terminal responsive to
the derivative reference signal and a non-inverting input terminal
responsive to said inverted signal, for producing a fourth comparison
signal;
and third OR gate means responsive to said third and fourth comparison
signals for producing the derivative threshold signal.
19. The memory nonlinear noise-blanking circuit of claim 11 wherein the
first predetermined time is equal to .DELTA.t.sub.1 plus the rise time of
the noise signal.
20. A memory nonlinear noise-blanking circuit responsive to a composite
signal including an information signal distorted by a noise signal, said
memory nonlinear noise-blanking circuit comprising:
delay means responsive to the composite signal for producing a delayed
signal;
means for producing a first reference signal;
threshold detector means responsive to said composite signal and said first
reference signal for producing a threshold signal, wherein said threshold
signal is in a first state when said composite signal exceeds said first
reference signal, and wherein said threshold signal is in a second state
when said composite signal does not exceed said first reference signal;
timer means responsive to said threshold signal for producing a timing
signal, wherein said timing signal is in a first state when said threshold
signal is in said first state and wherein said timing signal changes to a
second state a predetermined time after said threshold signal changes to
said second state;
first sample and hold circuit means having a data input terminal responsive
to said delayed signal and a control input terminal responsive to said
timing signal, for producing a first sampled signal at an output terminal
thereof, wherein while said timing signal is in said first state, said
first sampled signal is held constant at a value representative of the
value of said delayed signal when said timing signal changed to said first
state, and wherein while said timing signal is in said second state said
first sampled signal is representative of said delayed signal;
first differentiator means responsive to said delayed signal for producing
a first derivative signal;
second sample and hold circuit means having a data input terminal
responsive to said first derivative signal and a control input terminal
responsive to said timing signal, for producing a second sampled signal at
an output terminal thereof, wherein while said timing signal is in said
first state said second sampled signal is latched to the value of said
first derivative signal when said timing signal changed to said first
state, and wherein while said timing signal is in said second state said
second sampled signal is representative of said first derivative signal;
synthesis means responsive to said second sampled signal for producing an
estimate signal having a linear slope equal to the value of said first
derivative signal while said timing signal is in said first state;
and summer means responsive to said delayed signal and said first estimate
signal for producing an output signal such that said output signal
comprises said delayed signal plus said first estimate signal when said
timing signal is in said first state and said output signal comprises said
delayed signal when said timing signal is in said second state.
21. The memory nonlinear noise-blanking circuit of claim 20 wherein the
information signal is a digital signal.
22. The memory nonlinear noise-blanking circuit of claim 20 wherein the
information signal is an analog signal.
23. The memory nonlinear noise-blanking circuit of claim 20 wherein the
delay means is an analog delay line having a delay time of .DELTA.t.sub.1,
and wherein .DELTA.t.sub.1 is longer than the duration of the noise
signal.
24. The memory nonlinear noise-blanking circuit of claim 23 wherein the
analog delay line is a charge-coupled device.
25. The memory nonlinear noise-blanking circuit of claim 20 wherein the
magnitude of the first reference signal is greater than the magnitude of
the information signal, and wherein the magnitude of the first reference
signal is exceeded by the composite signal.
26. The memory nonlinear noise-blanking circuit of claim 20 wherein the
threshold detector means includes:
first comparator means having an inverting input terminal responsive to the
first reference signal and a non-inverting input terminal responsive to
the composite signal, for producing a first comparison signal;
inverter means responsive to the composite signal for producing an inverted
signal;
second comparator means having an inverting input terminal responsive to
the first reference signal and a non-inverting input terminal responsive
to the inverted signal for producing a second comparison signal;
and OR gate means responsive to said first output and said second
comparison signals, for producing the threshold signal at an output
terminal thereof.
27. The memory nonlinear noise-blanking circuit of claim 20 wherein the
predetermined time is equal to .DELTA.t.sub.1 plus the rise time of the
noise signal.
28. The memory nonlinear noise-blanking circuit of claim 20 including
disable means for clearing the synthesis means such that the estimate
signal has zero value when the timing signal is in the second state.
29. The memory non-linear noise-blanking circuit of claim 28 wherein the
synthesis means includes:
a constant-current source for producing a current determined by the second
sampled signal;
a capacitor connected in parallel with said constant-current source wherein
the voltage across said capacitor is the estimate signal.
30. The memory nonlinear noise-blanking circuit of claim 29 wherein the
disable means includes:
an inverting gate responsive to the timing signal for producing an inverted
signal having first and second states;
discharge means responsive to said inverted signal for discharging the
capacitor when the timing signal is in said first state, such that the
estimate signal has zero value.
31. The memory nonlinear noise-blanking circuit of claim 20 including:
second differentiator means responsive to the first derivative signal for
producing a second derivative signal;
third sample and hold circuit means having a data input terminal responsive
to said second derivative signal and a control input terminal responsive
to the timing signal, for producing a third sampled signal at an output
terminal thereof, wherein while the timing signal is in the first state
said third sampled signal is latched to the value of said second
derivative signal when the timing signal changed to said first state, and
wherein while the timing signal is in the second state said third sampled
signal is representative of said second derivative signal, and wherein the
synthesis means is responsive to said third sampled signal such that the
linear slope of the estimate signal changes in accord with said second
derivative signal.
32. A memory nonlinear noise-blanking circuit responsive to a composite
signal including an information signal distorted by a noise signal, said
memory nonlinear noise-blanking circuit comprising:
delay means responsive to the composite signal for producing a delayed
signal;
means for producing a first reference signal;
threshold detector means responsive to said composite signal and said first
reference signal for producing a threshold signal, wherein said threshold
signal is in a first state when said composite signal exceeds said first
reference signal, and wherein said threshold signal is in a second state
when said composite signal does not exceed said first reference signal;
timer means responsive to said threshold signal for producing a first
timing signal, wherein said first timing signal is in a first state when
said threshold signal is in said first state, and wherein said first
timing signal changes to a second state a first predetermined time after
said threshold signal changes to said second state;
one-shot multivibrator means responsive to said first timing signal for
producing a second timing signal, wherein said second timing signal is
triggered to a first state by the leading edge of said first timing signal
and wherein said second timing signal remains in said first state for a
second predetermined time, and wherein said second timing signal is in a
second state at all other times;
first sample and hold circuit means having a data input terminal responsive
to said delayed signal and a control input terminal responsive to said
timing signal, for producing a first sampled signal at an output terminal
thereof, wherein while said timing signal is in said first state said
first sampled signal is held constant at a value representative of the
value of said delayed signal when said timing signal changed to said first
state, and wherein while said timing signal is in said second state said
first sampled signal is representative of said delayed signal;
first differentiator means responsive to said first sampled signal for
producing a first derivative signal;
second sample and hold circuit means having a data input terminal
responsive to said first derivative signal and a control input terminal
responsive to said timing signal, for producing a second sampled signal at
an output terminal thereof, wherein while said timing signal is in said
first state said second sampled signal is latched to the value of said
first derivative signal when said timing signal changed to said first
state, and wherein while said timing signal is in said second state said
second sampled signal is representative of said first derivative signal;
synthesis means responsive to said second sampled signal for producing an
estimate signal having a linear slope equal to the value of said first
derivative signal while said second timing signal is in said first state;
and summer means responsive to said delayed signal and said first estimate
signal for producing an output signal such that said output signal
comprises said delayed signal plus said first estimate signal when said
timing signal is in said first state and said output signal comprises said
delayed signal when said timing signal is in said second state.
33. The memory nonlinear noise-blanking circuit of claim 32 wherein the
information signal is a digital signal.
34. The memory nonlinear noise-blanking circuit of claim 32 wherein the
information signal is an analog signal.
35. The memory nonlinear noise-blanking circuit of claim 32 wherein the
delay means is an analog delay line having a delay time of .DELTA.t.sub.1,
and wherein .DELTA.t.sub.1 is longer than the duration of the noise
signal.
36. The memory nonlinear noise-blanking circuit of claim 35 wherein the
analog delay line includes a charge-coupled device.
37. The memory nonlinear noise-blanking circuit of claim 35 wherein the
magnitude of the first reference signal is greater than the magnitude of
the information signal, and wherein the magnitude of the first reference
signal is exceeded by the composite signal.
38. The memory nonlinear noise-blanking circuit of claim 32 wherein the
threshold detector means includes:
first comparator means having an inverting input terminal responsive to the
first reference signal and a non-inverting input terminal responsive to
the composite signal for producing a first comparison signal;
inverter means responsive to the composite signal for producing an inverted
signal;
second comparator means having an inverting input terminal responsive to
the first reference signal and a non-inverting input terminal responsive
to the inverted signal for producing a second comparison signal;
and OR gate means responsive to said first and said second comparison
signals, for producing the threshold signal at an output terminal thereof.
39. The memory nonlinear noise-blanking circuit of claim 32 wherein the
first predetermined time is equal to .DELTA.t.sub.1 plus the rise time of
the noise signal.
40. The memory nonlinear noise-blanking circuit of claim 32 including
disable means for clearing the synthesis means such that the estimate
signal has zero value when the timing signal is in the second state.
41. The memory non-linear noise-blanking circuit of claim 40 wherein the
synthesis means includes:
a constant-current source for producing a current determined by the second
sampled signal;
a capacitor connected in parallel with said constant-current source wherein
the voltage across said capacitor is the estimate signal.
42. The memory nonlinear noise-blanking circuit of claim 41 wherein the
disable means includes:
an inverting gate responsive to the second timing signal for producing an
inverted signal having first and second states;
and discharge means responsive to said inverted signal for discharging the
capacitor when the second timing signal is in said first state, such that
the estimate signal has zero value.
43. The memory nonlinear noise-blanking circuit of claim 32 including:
second differentiator means responsive to the first derivative signal for
producing a second derivative signal;
third sample and hold means having a data input terminal responsive to said
second derivative signal and a control input terminal responsive to the
timing signal, for producing a third sampled signal at an output terminal
thereof, wherein while the timing signal is in the first state said third
sampled signal is latched to the value of said second derivative signal
when the timing signal changed to the first state, and wherein while the
timing signal is in the second state said third sampled signal is
representative of said second derivative signal, and wherein the synthesis
means is responsive to said third sampled signal such that the linear
slope of the estimate signal changes in accord with said second derivative
signal.
44. The memory nonlinear noise-blanking circuit of claim 32 including
bandpass filter means disposed between the first sample and hold circuit
means and the first differentiator means, wherein said bandpass filter
means is responsive to the first sampled signal for producing a filtered
signal, and wherein the first differentiator means is responsive to said
filtered signal.
45. A memory nonlinear noise-blanking circuit responsive to a composite
signal including an information signal distorted by a noise signal having
a period of .DELTA.t, said memory nonlinear noise-blanking circuit
comprising:
delay means responsive to the composite signal for producing a delayed
signal;
means for producing a first reference signal;
threshold detector means responsive to said composite signal and said first
reference signal for producing a threshold signal, wherein said threshold
signal is in a first state when said composite signal exceeds said first
reference signal, and wherein said threshold signal is in a second state
when said composite signal does not exceed said first reference;
timer means responsive to said threshold signal for producing a timing
signal, wherein said timing signal is in a first state when said threshold
signal is in said first state, and wherein said timing signal changes to a
second state a first predetermined time after said threshold signal has
returned to said second state;
first sample and hold means having a data input terminal responsive to said
delayed signal and a control input terminal responsive to said timing
signal for producing a first sampled signal at an output terminal thereof,
wherein while said timing signal is in said first state said first sampled
signal is held constant at a value respresentative of the value of said
delayed signal when said timing signal changed to said first state, and
wherein while said timing signal is in said second state said first
sampled signal is representative of said delayed signal;
first differentiator means responsive to said first sampled signal for
producing a first derivative signal;
first amplifier means responsive to said first derivative signal for
producing a first amplified signal, wherein said first amplifier means has
a gain of .DELTA.t;
second sample and hold means circuit having a data input terminal
responsive to said first amplified signal and a control input terminal
responsive to said first timing signal for producing a second sampled
signal at an output terminal thereof, wherein while said timing signal is
in said first state said second sampled signal is latched to the value of
said first amplified signal when said timing signal changed to said first
state, and wherein while said timing signal is in said second state said
second sampled signal is representative of said first amplified signal;
summer means responsive to said first and said second sampled signals for
producing an output signal such that said output signal comprises the sum
of said first and said second sampled signals.
46. The memory nonlinear noise-blanking circuit of claim 45 wherein the
information signal is a digital signal.
47. The memory nonlinear noise-blanking circuit of claim 45 wherein the
information signal is an analog signal.
48. The memory nonlinear noise-blanking circuit of claim 45 wherein the
delay means is an analog delay line having a delay time of .DELTA.t.sub.1,
and wherein .DELTA.t.sub.1 is longer than the duration of noise signal.
49. The memory nonlinear noise-blanking circuit of claim 45 wherein the
analog delay line includes a charge-coupled device.
50. The memory nonlinear noise-blanking circuit of claim 45 wherein the
magnitude of the first reference signal is greater than the magnitude of
the information signal, and wherein the magnitude of the first reference
signal is exceeded by the composite signal.
51. The memory nonlinear noise-blanking circuit of claim 45 wherein the
threshold detector means includes:
first comparator means having an inverting input terminal responsive to the
first reference signal and a non-inverting input terminal responsive to
the composite signal, for producing a first comparison signal;
inverter means responsive to the composite signal for producing an inverted
signal;
second comparator means having an inverting input terminal responsive to
the first reference signal and a non-inverting input terminal responsive
to the inverted signal for producing a second comparison signal;
and OR gate means responsive to said first and to said second comparison
signals, for producing the threshold signal at an output terminal thereof.
52. The memory nonlinear noise-blanking circuit of claim 45 wherein the
first predetermined time is equal to .DELTA.t.sub.1 plus the rise time of
the noise signal.
53. The memory nonlinear noise-blanking circuit of claim 45 including:
second differentiator means responsive to the first derivative signal for
producing a second derivative signal;
second amplifier means responsive to said second derivative signal for
producing a second amplified signal, wherein said second amplifier means
has a gain of (.DELTA.t).sup.2 /2!;
third sample and hold circuit means having a data input terminal responsive
to said second amplified signal and a control input terminal responsive to
the timing signal for producing a third sampled signal at an output
terminal thereof, wherein while said timing signal is in said first state
said third sampled signal is latched to the value of said second amplified
signal when said timing signal changed to said first state, and wherein
while said timing signal is in said second state said third sampled signal
is representative of said second amplified signal, and wherein said summer
means is responsive to said third sampled signal.
54. The memory nonlinear noise-blanking circuit of claim 45 including
bandpass filter means disposed between the first sample and hold circuit
means and the first differentiator means, wherein said bandpass filter
means is responsive to the first sampled signal for producing a filtered
signal, and wherein the first differentiator means is responsive to said
filtered signal.
55. A memory nonlinear noise-blanking circuit responsive to a composite
signal including an information signal distorted by a noise signal, said
memory nonlinear noise-blanking circuit comprising:
first delay means responsive to the composite signal for producing a
delayed signal, wherein the delayed signal lags the composite signal by a
first predetermined time;
predictor means responsive to said composite signal for producing a
prediction signal representative of the expected future trajectory of said
composite signal, wherein said predictor means has a predetermined lead
time;
means for producing a first reference signal;
first threshold detector means responsive to said composite, prediction,
and first reference signals for producing a first threshold signal,
wherein said first threshold signal is in a first state when the
difference between said composite and prediction signals exceeds said
first reference signal, and wherein said first threshold signal is in a
second state when the difference between said composite and prediction
signals does not exceed said first reference signal;
first timer means responsive to said first threshold signal for producing a
first timing signal, wherein said first timing signal is in a first state
when said first threshold signal is in said first state, and wherein said
first timing signal changes to a second state a second predetermined time
after said first threshold signal changes to said second state;
second delay means responsive to said prediction signal for producing a
delayed prediction signal, wherein the delayed prediction signal lags the
prediction signal by said first predetermined time;
and first gate means responsive to said delayed, first timing, and delayed
prediction signals for producing an output signal, wherein said output
signal represents said delayed prediction signal when said first timing
signal is in said first state, and represents said delayed signal when
said first timing signal is in said second state.
56. The memory nonlinear noise-blanking circuit of claim 55 wherein the
information signal is a digital signal.
57. The memory nonlinear noise-blanking circuit of claim 55 wherein the
information signal is an analog signal.
58. The memory nonlinear noise-blanking circuit of claim 55 wherein the
first delay means is an analog delay line having a delay time of
.DELTA.t.sub.1, and wherein .DELTA.t.sub.1 is longer than the duration of
the noise signal.
59. The memory nonlinear noise-blanking circuit of claim 58 wherein the
analog delay line includes a charge-coupled device.
60. The memory nonlinear noise-blanking circuit of claim 55 including:
means for producing a second reference signal;
second threshold detector means responsive to the composite signal and said
second reference signal for producing a second threshold signal, wherein
said second threshold signal is in a first state when the composite signal
exceeds said second reference signal and wherein said threshold signal is
in a second state when the composite signal does not exceed said second
reference signal;
second timer means responsive to said second threshold signal for producing
a second timing signal, wherein said second timing signal is in a first
state when said second threshold signal is in a first state, and wherein
said second timing signal changes to a second state a third predetermined
time after said second threshold signal changes to said second state;
sample and hold circuit means disposed between the first delay means and
the first gate means such that said sample and hold means is responsive to
the delayed signal at a data input terminal thereof, said sample and hold
circuit means having a control input terminal responsive to said second
timing signal, for producing a sampled signal at an output terminal
thereof, wherein while said second timing signal is in said first state
said sampled signal is held constant at a value representative of the
value of said delayed signal when said second timing signal changed to
said first state, and wherein while said second timing signal is in said
second state said sampled signal is representative of said delayed signal,
and wherein the first gate means is responsive to said sampled signal.
61. The memory nonlinear noise-blanking circuit of claim 60 wherein the
magnitude of the second reference signal is greater than the magnitude of
the information signal and wherein the magnitude of the second reference
signal is exceeded by the composite signal distorted by the noise signal.
62. The memory nonlinear noise-blanking circuit of claim 60 wherein the
second threshold detector means includes:
first comparator means having an inverting input terminal responsive to the
second reference signal and a non-inverting input terminal responsive to
the composite signal, for producing a first comparison signal;
inverter means responsive to the composite signal for producing an inverted
signal;
second comparator means having an inverting input terminal responsive to
the second reference signal and a non-inverting input terminal responsive
to said inverted signal for producing a second comparison signal;
and OR gate means responsive to said first and said second comparison
signals for producing the second threshold signal at an output terminal
thereof.
63. The memory nonlinear noise-blanking circuit of claim 60 wherein the
third predetermined time is equal to .DELTA.t.sub.1 plus the rate time of
the noise signal.
64. The memory nonlinear noise-blanking circuit of claim 60 including:
second gate means having a data input terminal responsive to the composite
signal and a control input terminal responsive to the second timing signal
for producing a first signal at an output terminal thereof, wherein said
first signal has zero magnitude when the second timing signal is in the
first state, and wherein said first signal is representative of the
composite signal when the second timing signal is in the second state;
bandpass filter means responsive to said first signal for producing a
filtered signal wherein said bandpass filter means has a predetermined
delay time;
and wherein the predictor means is disposed between said bandpass filter
means and the second delay means such that the predictor means is
responsive to said filtered signal, and such that the second delay means
is responsive to the prediction signal.
65. The memory nonlinear noise-blanking circuit of claim 55 wherein the
first threshold detector means includes:
summer means having an inverting input terminal responsive to the composite
signal and a non-inverting input terminal responsive to the prediction
signal for producing a difference signal representative of the difference
between the composite and the prediction signals;
first comparator means having an inverting input terminal responsive to the
first reference signal and a non-inverting input terminal responsive to
said difference signal, for producing a first comparison signal;
inverter means responsive to said difference signal for producing an
inverted signal;
second comparator means having an inverting input terminal responsive to
the first reference signal and a non-inverting input terminal responsive
to said inverted signal for producing a second comparison signal;
and gate means responsive to said first and said second comparison signals
for producing the first threshold signal at an output terminal thereof.
66. The memory nonlinear circuit of claim 58 including one-shot
multivibrator means disposed between the first timer means and the first
gate means, wherein said one-shot multivibrator means is responsive to the
first timing signal for producing a second timing signal, wherein said
second timing signal is triggered to a first state by a leading edge of
the first timing signal and wherein said second timing signal remains in
said first state for a fourth predetermined time, and wherein said second
timing signal is in a second state at all other times and wherein the
first gate means is responsive to said second timing signal.
67. The memory nonlinear noise-blanking circuit of claim 55 wherein the
second delay means is an analog delay line having a delay time of
.DELTA.t.sub.1.
68. The memory nonlinear noise-blanking circuit of claim 67 wherein the
analog delay line includes a charge-coupled device. |
|
 |
|
 |
Claims |
|
