Method and apparatus for baseband tracking of a PN code sequence in a spread spectrum receiver

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TECHNICAL FIELD

The present invention relates generally to the detection of spread spectrum communication signals and more particularly to a baseband tracking loop for synchronizing the pseudonoise (PN) code sequence of a received spread spectrum signal to a local PN code sequence.

BACKGROUND OF THE INVENTION

In a spread spectrum communication system, the spread spectrum signal may be formed by phase modulating a narrowband signal by a pseudonoise (PN) code sequence. In such systems, effective recovery of the narrowband signal at the receiver requires synchronization between the received signal's PN code sequence and a local PN code sequence used to correlate the received signal. In prior art spread spectrum communication systems, synchronization tracking is usually performed by measuring the correlation at early and late times and forming a time discrimination function from such measurements to control the receiver's reference timing. However, since most spread spectrum systems correlate the received spread signal at RF, such "delay-lock" loop tracking schemes have utilized costly RF components. A baseband approach to the synchronization of the local and received PN code sequences is therefore desirable.

SUMMARY OF THE INVENTION

The present invention describes a baseband approach to the synchronization of the local and received PN code sequences in a spread spectrum communication system. In accordance with the invention, a baseband tracking loop comprises a phase comparator for translating the received spread spectrum signal to baseband to produce an I (in-phase) channel baseband signal and a Q (quadrature-phase) channel baseband signal. A data baseband correlator correlates the I channel and Q channel baseband signals with in-phase and quadrature-phase PN signals incorporating the local PN code sequence to produce despread on-time I channel and Q channel baseband signals. Similarly, an error baseband correlator is provided for correlating the I channel and Q channel baseband signals with advanced and delayed versions of the in-phase and quadrature-phase PN signals incorporating the local PN code sequence to produce despread advanced and delayed I channel and Q channel baseband signals.

The on-time, advanced and delayed I channel and Q channel baseband signals are processed and then combined to produce an error signal proportional to a difference between the local PN code sequence and the received PN code sequence. A numerically-controlled oscillator circuit is responsive to the error signal for forming a local PN clock signal from a reference PN clock signal, the local PN clock signal being used to control the reading of the local PN code sequence. In operation, the rate of reading the local PN code sequence is accelerated or retarded to synchronize the local and received PN code sequences.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present invention and the advantages thereof, reference is now made to the following Description taken in conjunction with the accompanying Drawings in which:

FIG. 1 is a block diagram illustrating the baseband tracking loop of the present invention for synchronizing a local PN code sequence with a received PN code sequence incorporated in a received spread spectrum signal.

FIG. 2 is a block diagram of the numerically-controlled oscillator of FIG. 1 for advancing or delaying the phase of the reference PN clock signal.

FIG. 3 is an illustration of waveforms which are present in the circuit of FIG. 1 when the received PN code sequence is synchronized to the local PN code sequence.

FIGS. 4 and 5 illustrate the waveforms for the circuit of FIG. 1 when the received PN code sequence is delayed or advanced, respectively, with respect to the local PN code sequence.

FIG. 6 is an illustration of signal waveforms for the numerically-controlled oscillator circuit of FIG. 2.

FIG. 7 is a block diagram showing the structure of the baseband down converter and one of the baseband correlators of FIG. 1.

DETAILED DESCRIPTION

Referring now to the drawings in which like reference characters designate like or corresponding parts throughout the several figures, FIG. 1 shows a block diagram of the baseband tracking loop of the present invention. As is well known in the prior art, a spread spectrum signal may be formed by phase modulating a narrowband signal by a pseudonoise (PN) code sequence. In such systems, effective recovery of the narrowband signal at the receiver requires synchronization between the received signal's PN code sequence and a local PN code sequence used to correlate the received signal. It is known in the prior art to perform synchronization tracking by measuring the correlation at early and late times and forming a time discrimination function from each measurements to control the receiver's reference timing. As will be described in more detail below, the baseband tracking loop of the present invention also serves to measure the correlation at early and late times to form an error function to control the receiver's reference timing. However, in contradistinction to such loop tracking schemes which utilize costly RF components, the tracking loop of the present invention operates at baseband.

Referring now to FIG. 1, the baseband tracking loop 10 includes a baseband down converter 12 connected to receive the IF spread specrum signal S(t) via line 14. As described above, this signal includes a PN code sequence which is used to phase modulate a narrowband signal at the spread spectrum transmitter. The baseband down converter 12 also receives a local oscillator signal LO via line 16. In operation, the baseband down converter 12 provides a phase comparison between the IF spread spectrum signal and the local oscillator signal to produce a difference I channel (in-phase) spread baseband signal designated I.sub.S on line 18, and a difference Q channel quadrature-phase) spead baseband signal designated Q.sub.S on a line 20.

The I channel and Q channel spread baseband signals are applied via lines 18 and 20 to a data baseband correlator 22. These signals are also applied via lines 24 and 26 to an error baseband correlator 28. The data baseband correlator 22 and the error baseband correlator 28 also receive input signals via buses 32 and 33, respectively. In particular, a local PN code sequence occurring early in time is applied to an elastic delay/channelizer circuit 34 via line 34. The local PN code sequence is the same as the PN code sequence incorporated into the transmitted spread spectrum signal. However, this local PN code sequence may be phase or frequency displaced from the received PN code sequence, thereby preventing effective correlation of the received spread spectrum signal. As will be described in more detail below, the baseband tracking loop 10 of the present invention serves to synchronize the local PN code sequence with the received PN code sequence. Referring back to FIG. 1, the elastic delay/channelizer circuit 34 also receives a reference PN clock signal via line 38 and a local PN clock signal via line 40. In response to a READ pulse received via line 41, the elastic delay/channelizer circuit 34 produces I channel and Q channel PN signals delayed within .+-.1 bit of the proper amount incorporating the local PN code sequences which are output on bus 30 and applied to the bit delay circuit 31. The bit delay circuit 31 delays the I channel and Q channel PN signals by different bit times to produce the on-time PN signals which are applied to the data baseband correlator 22 via bus 32, and the advanced and delayed PN signals which are applied to the error baseband correlator 28 via bus 33. More specifically bit delay circuit 31 delays the advanced PN signals by 1 bit, the on-time PN signals by 2 bits and the delayed PN signals by 3 bits.

The data baseband correlator 22 correlates the I channel and Q channel baseband signals I.sub.S and Q.sub.S with the on-time I channel and Q channel PN signals to produce despread on-time I channel and Q channel baseband signals, I.sub.B and Q.sub.B, on lines 42 and 44. Likewise, the error baseband correlator 28 correlates the I channel and Q channel baseband signals I.sub.S and Q.sub.S with the advanced and delayed I channel and Q channel PN signals to produce despread advanced and delayed I channel and Q channel baseband signals, I.sub.BE and Q.sub.BE, on lines 46 and 48. The on-time, advanced and delayed I channel and Q channel baseband signals on lines 42, 44, 46 and 48 are then supplied to a signal processing circuit 50 which provides appropriate filtering and gain control, as is well known in the prior art. In particular, where digital baseband data is being transmitted, the signal processing circuit 50 provides matched filtering through integrate and dump circuits. For analog baseband data, active or passive low pass filtering can be utilized. The signal processing circuit 50 also includes an automatic gain control circuit (for analog data) or a hard limiter circuit (for digital data) to insure that the signals applied to the remainder of the circuit are relatively insensitive to amplitude changes in the received spread spectrum signal. The processed on-time I channel and Q channel baseband signals form a data channel output from the signal processing circuit 50. Similarly, the processed advanced or delayed I channel and Q channel baseband signals from an error channel output from the signal processing circuit 50.

The data channel and error channel outputs from the signal processing circuit 50 are applied to the complex multiplier circuits 52 and 54. In particular, multiplier 52 receives the inphase outputs from the signal processing circuit while multiplier 54 receives the quadrature-phase outputs therefrom. The multipliers 52 and 54 produce outputs on lines 56 and 58 which are summed by summer 60 to produce an error signal E(t) on line 62. The error signal E(t) is proportional to a difference in a signal characteristic, e.g., the frequency or phase, of the local PN code sequence with respect to the received PN code sequence. Such a difference prevents proper correlation of the received spread spectrum signal. To ameloriate this problem, the error signal E(t) is supplied to a loop filter 64 which smoothes the signal to a D.C. level. The output of the loop filter 64 is supplied via line 66 to an analog-to-digital converter (A/D) 68 where a ten bit binary number is generated and supplied via bus 70 to a numerically-controlled oscillator 72. The numerically-controlled oscillator 72 receives the reference PN clock signal as an input via line 39 and produces the local PN clock signal as an output on line 40. As will be described in more detail below, the numerically-controller oscillator 72 advances or delays the phase of the reference PN clock signal to synchronize the local and received PN code sequences. In particular, the local PN clock signal controls the application of a READ pulse to the elastic delay/channelizer circuit 34 and thus controls the rate of reading the local PN code sequence.

Referring now to FIG. 2, the numerically-controlled oscillator 72 of FIG. 1 is shown in detail. In particular, the ten bit binary number representing the error signal E(t) is supplied via bus 70 to a twelve bit full adder 74 which is connected via bus 76 to a 12 bit accumulator 78. The output of the accumulator 78 is supplied back to the adder via bus 79. The most significant bit (MSB) and sign bit of the output value of adder 74 are supplied via bus 80 to an overflow detector 82. The sign bit is also supplied to the up-down counter 84. The overflow detector 82 senses the MSB each time the accumulator 78 overflows. The output of the overflow detecter clocks the updown counter 84 while the sign bit controls the direction of the count. The output of the up-down counter is supplied via a four bit bus 86 to a multiplexer 88. As seen in FIG. 2, the reference PN clock signal is supplied via line 39 to a ten bit tapped digital delay line 90 which is connected by a ten bit bus 92 to the multiplexer 88. As will be described in more detail below, the rate of overflow of the adder 74 is directly proportional to the magnitude of the error signal E(t) applied to the analog-to-digital converter 68 of FIG. 1. The output of the up-down counter 84 provides for advancing or retarding of the phase of the reference PN clock signal by selecting the proper delay tap of the delay line 90. The adjusted reference PN clock signal is applied to one input of an exclusive-OR gate 94, the other input thereto being the carry output of the up-down counter 84 which is divided by two by the divide circuit 96. The numerically-controller oscillator 72 provides for advancing or retarding the phase of the reference PN clock signal in increments of 1/20th (1/2 due to divide circuit 96.times.1/10 due to delay line 90) of the clock period. The output of the exclusive-OR gate 94 is filtered by bandpass filter 97 and limited by the threshold device 98 to form the local PN clock signal which is output on line 40. As noted above, the local PN clock signal is applied to the elastic delay/channelizer circuit 34 of FIG. 1 to control the application of the READ pulse thereto and thus the rate of reading the local PN code sequence used to correlate the received spread spectrum signal.

Referring now to FIGS. 3-6, the operation of the baseband tracking loop of the present invention will be described in detail. As noted above, effective recovery of the narrowband signal at the spread spectrum receiver requires synchronization between the received signal's PN code sequence and the local PN code sequence used to correlate the received signal. In the case where such synchronization exists, the output of the data baseband correlator 22 will be optimal and there will be no output from the error baseband correlator 28. This condition is shown in FIG. 3 for the I channel of the system. Each waveform in FIG. 3 is labeled by the line which carries the signal. As can be seen, when the received signal's PN code sequence and the local PN code sequence are synchronized, there is no error voltage present on line 66 from the output of the loop filter 64. Therefore, the numerically-controlled oscillator 72 does not advance or retard the reference PN clock signal used to generate the local PN clock signal.

FIG. 4 shows the condition where the received PN code sequence is delayed relative to the local PN code sequence. In this case, both the data baseband correlator 22 and the error baseband correlator 28 produce outputs. These output signals are 180.degree. out of phase in the case where the received PN code sequence is late relative to the local PN code sequence. This 180.degree. phase differential produces a negative error voltage on line 66. Referring simultaneously to FIGS. 1, 2 and 4, this negative error voltage is then applied to the A/D converter 68 where a ten bit binary number is generated and supplied to the numerically-controlled oscillator 72. In operation, this negative binary number is periodically added to the accumulator 78 to bring the total stored therein to become less positive, reducing the overflow rate detected by the overflow detector 82. As noted above, the rate of overflow is directly proportional to the magnitude of the negative error voltage on line 66. Moreover, the change in the sign bit from positive to negative due to the negative error voltage on line 66 will cause the up-down counter 84 to change directions so that progressively longer delays on the tapped digital delay line 90 are selected by the multiplexer 88. Referring briefly to FIG. 6, there is shown an illustration of the tapped delay line outputs. As can be seen, the phase of the reference PN clock signal may be advanced or delayed by the tapped delay line to one of ten values, TAP1-TAP10. The exclusive-OR gate 94 provides the waveforms TAP1-TAP10 by acting as a programmable inverter controlled by the carry output of the up-down counter 84. The tapped delay line and exclusive-OR gate thus provide increments of 1/20th of the PN clock signal.

Therefore, it can be seen that in response to the negative error voltage on line 66, the reference PN clock signal on line 39 is delayed by the numerically-controlled oscillator 72. The local PN clock signal on line 40 is now fed back to the elastic delay/channelizer circuit 34 to control the application of the READ pulse thereto. The elastic delay then serves to retard the rate of reading the local PN code sequence. This correction in phase of the local PN code sequence will act to optimize on-time correlation by allowing the received PN code sequence in the spread baseband signal to "catch-up" to the local PN code sequence. When these PN code sequences are synchronized, the output from the baseband error correlator 28 due to correlation with the delayed local PN code sequence will drop to zero. The output of multiplier 52 will also drop to zero as will the binary number applied to the numerically-controlled oscillator 72. As the error signal becomes zero, the adder 74 stops overflowing and therefore, the up-down counter 84 selects one particular reference PN clock pulse delay and thus introduces no further frequency shift. Therefore, in the absence of any further distrubance in the received PN code sequence's frequency or phase, on-time correlation remains optimized.

FIG. 5 shows the I channel signal waveforms for the case where the received PN code sequence is ahead of the local PN code sequence. In this case, the error baseband correlator 28 yields an output which is in phase with the data baseband correlator output on line 42. When these two signals are multiplied by complex multiplier 52, a positive error voltage results on line 66. This causes a positive binary number to be supplied to the adder 74 which changes the rate of overflow detected by the overflow detector 82. The positive error voltage on line 66 will eventually cause the sign bit to change the direction of the up-down counter 84 such that progressively shorter delays are selected from the tapped digital delay line 90 by the multiplexer 88. This effectively increases the frequency of the reference PN clock signal on line 39 by continuously advancing its phase.

The local PN clock signal on line 49 is now applied to the elastic delay/channelizer circuit 34 to control the application of the READ pulse thereto. The elastic delay then serves to accelerate the reading of the local PN code sequence to allow the sequence to "catch-up" with the received PN code sequence. Once optimal on-time correlation is again established, the error voltage on line 66 drops to zero. Therefore, the accumulator 78 stops overflowing and the up-down counter 84 selects one particular reference PN clock phase delay and thus introduces no further frequency shift. Therefore, in the absence of any further distrubance in the received PN code sequence's frequency or phase, on-time correlation remains optimized.

It should be noted that the waveforms shown in FIGS. 4 and 5 only illustrate the I channel of the spread spectrum system. It should be appreciated that the Q channel of the system also provides similar outputs on line 58 which are reflected in the error signal E(t) on line 66. It should also be recognized that the above examples of errors due to early and late arrival of the received spread baseband signal involve adjustment to realign the reference PN clock phase. However, if a continuous frequency error exists between the local and received PN code sequences, the baseband tracking loop 10 will also compensate for each error by continuously rotating the reference PN clock phase forward or back such that frequency and phase are matched.

Referring now to FIG. 7, the baseband down converter 12 and the data baseband correlator 22 of FIG. 1 will now be described in detail. These components of the baseband tracking loop 10 have been described in copending application Ser. No. 434,530 entitled, "Method and Apparatus for Despreading a Spread Spectrum Signal at Baseband," to Mosley, et al. With reference to FIG. 7, the baseband down converter 12 comprises a phase comparator 114 and tracking AGC amplifiers 122 and 126. The phase comparator receives the IF spread spectrum input signal S(t) incorporating the received PN code sequence via the line 14. The local oscillator signal LO is also input via the line 16 to the phase comparator 114. The spread IF input signal is phase compared (mixed) with the local oscillator signal to produce the I channel (in-phase) spread baseband signal designated I.sub.S at a line 118. The phase comparator 114 also produces a 90.degree. phase offset local oscillator signal which is phase compared to the spread IF input signal to produce the Q channel (quadrature-phase) spread baseband signal designated Q.sub.S at a line 120.

Signal I.sub.S is passed through the tracking AGC amplifier 122 to the line 18. Signal Q.sub.S is passed through the tracking AGC amplifier 126 to the line 20. An ACG control signal is input through a line 130 to regulate the amplitude of the signals at lines 18 and 20. The AGC control signal is produced by an amplitude monitor (not shown) which monitors the amplitude of the baseband I channel and Q channel signals produced by the data baseband correlator 22. The amplifiers 122 and 126 are matched for tracking such that the phase and the amplitude of the signals I.sub.S and Q.sub.S are balanced.

The data baseband correlator 22 includes a group of eight sample and hold circuits which are labeled 134, 136, 138, 140, 142, 144, 146 and 148. The I.sub.S signal at line 18 is provided at the input to each of the sample and hold circuits 134, 136, 138 and 140. The Q.sub.S signal at line 20 is provided as the input to the sample and hold circuits 142, 144, 146 and 148. A channelizer circuit 116 which forms part of the elastic delay/channelizer circuit 34 of FIG. 1, is provided for converting the local-phase PN code sequence on line 36 into a four-phase signal. The channelizer 116, which is described in detail in the above-referenced patent application, produces four signals which are transmitted via lines 117, 119, 121 and 123 to the one bit delays 31. The lines 117, 119, 121 and 123 form the data bus 30 seen in FIG. 1. The channelizer produces an inphase PN signal I.sub.PN on line 117. The logical inverse of the inphase PN signal, I.sub.PN, is produced at line 119. A quadrature phase PN signal Q.sub.PN is produced at line 121. The logical inverse of the quadrature-phase PN signal, Q.sub.PN, is produced at line 123.

The signal I.sub.PN on line 117 is delayed in circuit 31 and provided to the control inputs of sample and hold circuits 134 and 142 via line 125. The signal I.sub.PN on line 119 is delayed in circuit 31 and provided to the control inputs of sample and hold circuits 136 and 144 via line 127. Similarly, the signal Q.sub.PN on line 121 is delayed and provided to the control inputs of sample and hold circuits 138 and 146 via line 129. The signal Q.sub.PN on line 123 is delayed and provided to the control inputs of sample and hold circuits 140 and 148 via line 131. The lines 125, 127, 129 and 131 form the data bus 32 seen in FIG. 1. The outputs of sample and hold circuits 134-148 are transmitted respectively through lines 170, 172, 174, 176, 178, 180, 182 and 184. Lines 170 and 172 provide inputs to a summer 186. The output of sample and hold circuit 136 is the negative input of summer 186. The lines 174 and 176 provide inputs to a summer 188. The out