The dynamic semiconductor memory which has at least one block of memory (WLB), in which s block of memory has in each case a plurality of bit line blocks (TB, TB' . . . ) which has for each bit line block a local SAN driver (LTN), and possibly also a local SAP driver (LTP) for driving the read amplifiers (LV) belonging to this bit line block (TB), in order to avoid interfering voltage drops on long driver lines, and which has, to achieve an optimized drive function, multi-stage local SAN drivers (LTN) or SAP drivers (LTP) whose transistors generally have different channel widths.

Memory cells in a dynamic random access memory are coupled to bit lines which are coupled to sense amplifiers. Memory cells are enabled by an enabled word line which causes the memory cells to output data onto the bit lines to which they are coupled. A selected bit line is coupled to a data line while the sense amplifier is amplifying the signal provided by the memory cell. The effect of coupling the bit line to the data line is to hinder the refresh of the selected memory cell because the bit line does not reach full power supply voltage due to the loading by the data line. Full refresh is obtained by keeping the word line enabled for a predetermined time following the bit line being decoupled from the data line so the sense amplifier can bring the bit line to full power supply potential.

A MOS dynamic type RAM comprises memory cells (10), dummy cells (11), bit line pairs (BL, BL), word lines (WL), dummy word lines (DWL) and sense amplifiers (12). In a non-active cycle, the potentials of each pair of bit lines (BL, BL) are precharged at 1/2 of a supply potential V.sub.CC. Each sense amplifier (12) operates in an active cycle following the non-active cycle, while each active pull-up circuit (13) pulls up the potential of a higher level one of the pair of bit lines to V.sub.CC. This active cycle is defined by an internal RAS internal signal, which is generated by a NAND circuit (27) in response to an external RAS signal and an RPW signal obtained by delaying the external RAS signal by a delay circuit (20) and having a trailing edge obtained by delaying the trailing edge of the external RAS signal by a prescribed period.

Disclosed is a semiconductor memory device having a circuit integrally comprising both functions as the sense amplifier circuit for operating when reading out data from the memory cell and as the drive circuit for operating when writing data into the memory cell. By such structure, fast and stable operation of the semiconductor memory device is realized, and the area of the portions corresponding to the sense amplifier circuit and drive circuit can be reduced, so that higher density and higher degree of integration of semiconductor memory device may be realized.

A distributed control circuit for a sense amplifier is provided in which each sense amplifier has a pair of sensing control transistors connected in serial with each sensing node of the sense amplifiers. Each gate of the sensing control transistors has a respective resistor connected in sequence from the gate of the uppermost sensing control transistor to the gate of the lowermost sensing transistor. A delay compensation resistor is connected by the unit of a sensing control transistor group having the number of the sensing control transistors as many as an integer k.