 |
Description  |
|
|
1. Field of the Invention.
The invention relates to fusible links, particularly links for
metal-oxide-semiconductor (MOS) integrated circuits.
2. Prior Art.
In integrated circuits including MOS integrated circuits, there is often a
need for discretionary connections which, once completed, permanently
remain. These connections are sometimes made by opening a current path, as
well as by closing a current path. Such discretionary connections are
used, for example, to program read-only memories (ROMs), for programming
redundant circuits in memories, for selecting useful circuits in wafer
scale integration and for enabling features or disabling features in
integrated circuits.
In some cases, electrically programmable and electrically erasable
read-only memory (E2PROM) devices are employed for discretionary
connections. These E2PROM devices are most useful when used as part of an
E2PROM since then they may be readily fabricated with the memory.
Electrically programmable read-only memory cells are more difficult to use
since when used as part of an EPROM, they erase when the memory array is
erased. A structure for preventing such erasure is described in "Light
Shielded EPROM Cell", Ser. No. 389,415, filed June 17, 1982. This
copending application is assigned to the assignee of the present
application.
Most often, discretionary connections are made through use of fusible
links. These links, when fabricated, provide a closed connection and are
selectively "melted" to provide an open connection. In some cases, an
electrical current is passed through the fusible link causing it to open.
In other cases, a laser beam is used to melt the link. Examples of fusible
links and related art are described in U.S. Pat. Nos. 3,792,319;
3,699,395; 3,699,403; 3,028,659; 3,191,151; 3,555,365; 3,564,354 and
3,570,114.
One problem with fusible links is that oxygen is generally required to burn
or open a link. Thus the links are exposed to the air at the time the
discretionary connections are made. Openings through the integrated
circuits' passivation layer are used to expose the link to the atmosphere.
These openings make the circuit more difficult to use in plastic packages
since moisture is more likely to enter the circuit through these openings.
Also, since the links are exposed to the atmosphere when blown, the
discretionary connections are made at wafer sort, that is, prior to
packaging. This prevents, for instance, programming redundant elements in
the field to replace failed elements.
As will be seen, the present invention provides a fusible link in the form
of a capacitor like structure. The structure can be fabricated with
smaller geometries than prior art fusible links and, moreover, does not
require oxygen to make the connections. Thus, the connections can be made
with a complete passivation layer in place. This makes the integrated
circuit more compatible with plastic packages and enables connections to
be made after packaging in the field.
SUMMARY OF THE INVENTION
A capacitor-like, fusible link is described which is particularly useful
for an integrated circuit formed on a silicon substrate. An insulative
layer is formed on the substrate and an electrode is formed over this
insulative layer. A current path disposed within the substrate extends
beneath the insulative layer such that an electrical potential can be
imposed across the insulative layer (between the current path and the
electrode). Circuit means for selectively applying a potential across the
insulative layer is provided. This potential is of sufficient magnitude to
permanently deform the insulative layer so as to cause it to provide a
permanent conductor between the current path and electrode. It is believed
that silicon from the substrate or silicon from the electrode where a
polysilicon electrode is used melts into pin holes in the insulative layer
to provide the conductor.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a cross-sectional elevation view of a substrate illustrating the
presently preferred embodiment of the capacitor-like fusible link of the
present invention.
FIG. 2 is an electrical schematic showing the fusible link of the present
invention as part of an integrated circuit, and more particularly, as part
of a programming means for a redundant circuit.
DETAILED DESCRIPTION OF THE INVENTION
A fusible link in the form of a capacitor-like structure particularly
useful in MOS circuits is described. In the following description,
numerous specific details are set forth such as specific conductivity
types in order to provide a thorough understanding of the presently
preferred embodiment. It will be obvious to one skilled in the art,
however, that the present invention may be practiced without these
specific details. In other instances, well-known processing and structures
have not been described in detail in order not to unnecessarily obscure
the present invention.
Referring now to FIG. 1, the fusible link of the present invention is
fabricated on a silicon substrate 10. In the presently preferred
embodiment, the substrate is a p-type substrate and doped to a level of
approximately 50 ohm-cm.. The fusible link is formed between field oxide
regions 12 which regions are initially fabricated on the substrate in a
well-known manner.
The fusible link comprises the capacitor-like structure having an electrode
18, an insulative layer 17 and a lower electrode which comprises a current
path in the substrate 10. This path includes the n-type region 16 which is
contiguous with the n+ region 14.
In the presently preferred embodiment, the insulative layer 17 comprises
silicon dioxide which is grown on the substrate 10. This layer is between
50A-150A thick for reasons which will be described. The doped region 16 is
ion implanted through this oxide layer with arsenic or phosphorus to a
level of 1.times.1014/cm.sup.2. The electrode 18 is fabricated from
polysilicon and in the presently preferred embodiment is approximately
5500A thick. The region 14 which is contiguous with region 16 is doped
when the source/drain regions for the integrated circuit are formed. In
its preferred embodiment, arsenic ion implantation is used to form the
region 14 in alignment with the polysilicon electrode 18 (a doping level
in the range of 1015/cm.sup.2 is employed). The lines 15 and 20 are in
practice realized as well-known metal contacts and as will be seen, permit
a potential to be applied across the oxide layer 17 since the polysilicon
electrode 18 is completely insulated from the substrate by layer 17 and
the field oxide regions 12.
The entire structure using current production MOS processing is
approximately 3 microns by 3 microns. A separate masking step is employed
to obtain the layer 17 since the oxide in this layer is thinner than that
generally used in the remainder of the integrated circuit. The electrode
18 is fabricated from a polysilicon layer, which layer is used to form
gates, etc. for the integrated circuit. Electrode 18 may be fabricated
from a first layer of polysilicon or from a second layer of polysilicon.
To make the discretionary connection between the lines 15 and 20 a
potential is applied across these lines of sufficient magnitude to cause
the oxide layer 17 to rupture. It is believed that conduction begins at
the thinnest part of the oxide causing local heating. Then silicon from
the substrate or polysilicon electrode melts to form a thin filament
through pin holes in the oxide layer.
As mentioned, for the embodiment of FIG. 1, the oxide layer 17 is between
50A and 150A thick. In a typical integrated circuit using current MOS
technology, the gate oxides for MOS devices are typically 250A thick.
Approximately 10 to 20 volts is required to rupture the thinner oxide 17.
This voltage may be handled by the transistors in the integrated circuit
without damaging them. Thus, the 10-20 volts required to rupture oxide 17
may be coupled through the integrated circuit and selectively applied to
those links which require fusing.
It has been learned that the fusing of the fusible link shown in FIG. 1
must be done with reasonable care. More particularly, it has been learned
that, for the shown embodiment, 10-20 volts (DC) when applied through a
resistor having approximately 1K ohm resistance, provides the most
effective means for fusing the link. Test data has shown that where the
oxide layer is approximately 100A thick and has an area between 10 to 500
(micro m).sup.2, fusion occurred at a voltage of 12 to 16 volts. The
current required to cause this fusion is less than 0.1 microamps per micro
m.sup.2 of capacitor area. The fused link has a resistance of
approximately 0.5 to 2K ohms. A link, once fused, can handle currents of
up to 100 milliamps at room temperature for approximately a second before
it heals to an open fuse. Taking into account electron migration wear-out,
the predicted wear-out lifetime of a link, once fused, is substantially
greater than 3.times.10.sup.8 hours.
In FIG. 2, the link 22 is shown as part of a redundancy circuit. These
circuits are often used to enable redundant columns or rows in memories.
The redundant columns or rows replace defective columns or rows once
circuitry on the integrated circuit is programmed to recognize the address
of the defective column or row and cause the redundant column or row to be
selected in its place. A "Redundant Memory Circuit" is shown in U.S. Pat.
No,. 4,250,570.
The capacitor-like fusible link of the present invention is shown as link
22 in FIG. 2. Line 20 is connected to a current/voltage limiter 24 and
also to a resistor 25. This resistor in the presently preferred embodiment
is external to the integrated circuit and has a resistance of
approximately 1K ohms as previously mentioned. Resistor 25 interconnects
link 22 with the "programming" potential, which is in the range of 10 to
20 volts depending on the oxide thickness used in the link. After fusing
(programming), the resistor 25 and the potential V.sub.pp are of course
not required. During normal (non-programming) operation of the integrated
circuit the current/voltage limiter 24 interconnects the link 22 with the
VCC potential to prevent a high potential or large current surge from
inadvertently damaging the link 22 during normal operation. Ordinary
current/voltage limiting means are used for limiter 24.
The line 15 which is common with node 34 of the circuit of FIG. 2 is
coupled through transistor 30 to the potential V.sub.pp /2 (node 33)
during programming. Otherwise (during normal use) node 33 is coupled to
ground potential. The depletion mode transistor 30 assures that the node
34 is drawn to ground potential during normal operation if the link 22 is
open (not fused). If the link 22 is "shortened" (fused) node 34 is a
V.sub.CC during normal operation causing transistor 27 to conduct. Node 34
is also selectively coupled to ground through the enhancement mode
transistor 31 for purposes of fusing the link 22. The node 34 controls a
latch which comprises the transistors 26, 27 and 28 during normal
operation.
Assume first that the link 22 is open, that is, its oxide layer is not
ruptured. During the programming mode, the programming potential is
applied to link 22 through resistor 25. (The V.sub.pp potential is
typically applied to a plurality of links in the integrated circuit
through resistor 25.) Node 34 remains at V.sub.pp /2 since node 33 is at
that potential. The potential across the link (V.sub.pp /2) is not great
enough to fuse the link. So long as transistor 31 does not conduct, the
link remains open. Now if a a potential is applied to the redundancy
select line, (gate of transistor 31) node 34 is brought to ground
potential. This causes a sufficient voltage to be applied across link 22
to fuse it. As mentioned, the resistor 25 assures that the current through
the link is large enough to leave a conductive path, and yet not so large
as to cause an open circuit.
If the link 22 is open, node 34 remains at ground potential since node 33
is coupled to ground potential in normal use. Transistor 27 does not
conduct and the output line is drawn to V.sub.cc through transistor 26. On
the other hand, if the link 22 has been fused, node 34 is drawn to
V.sub.cc potential through the current/voltage limiter 24. (Transistor 30
does not conduct enough to draw the node 34 to ground potential.) With
node 34 close to the V.sub.cc potential, transistor 27 conducts while
transistor 28 is prevented from conducting. For this condition, the output
line is low.
The structure of FIG. 1, although shown used in a redundancy circuit in
FIG. 2 may be used in other circuits, such as read-only memories and other
applications as mentioned in the prior art section of this application.
While in the presently preferred embodiment a silicon dioxide layer 17 is
used, other insulative layers may be used such as a nitrodized oxide layer
or a silicon nitride layer. In some applications, it may be desirable to
have a silicon dioxide layer for the layer 17 while employing other
insulative layers such as silicon nitride to insulate the gates of the
field-effect transistors from the substrate. In this event, since the
silicon nitride has a higher break-down potential, it may in fact be
thinner than the layer 17, although its breakdown potential will be higher
than that associated with layer 17.
Thus, a capacitor-like structure which provides a fusible link has been
disclosed. The structure does not require oxygen to fuse the link and
thus, programming can occur after the formation of a passivation layer.
* * * * *
|
|
 |
|
 |
Description |
|
