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Description  |
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DESCRIPTION
1. Technical Field
This invention relates to debounce circuitry and more particularly to
debounce circuitry for providing synchronously clocked digital signals.
More particularly still, the invention relates to improved debounce
circuitry for providing debounced, synchronously clocked digital signals
from a single throw switch.
2. Background Art
Electromechanical switches characteristically "bounce" upon activation.
This "bounce" results in multiple pulses being supplied to the logic
circuits interfaced with the switches, and may cause erroneous operation
of the circuitry as a result. One previous method of eliminating this
"bounce" problem has involved the analog timing, i.e., RC time constants,
to filter the bounce frequency. Another prior technique for eliminating
"bounce" has been the use of an SR latch in combination with a single pole
double throw (SPDT) input switch configuration. In this latter regard, a
pair of cross-coupled NAND gates are alternately connected with the switch
contact in one or the other of its two "double throw" actuated positions.
This technique, of course, requires the utilization of an SPDT switch,
which may by more costly than a simpler switch such as a single pole,
single throw switch (SPST).
Even following removal of the multiple edges from the input signals by the
aforementioned debounce circuits, most digital circuits to which the
signals are being supplied still require them to be synchronized to an
internal clock before they can be combined with internal logic signals.
DISCLOSURE OF THE INVENTION
One object of the present invention is to provide an improved debouncer
circuit for use with a single-throw input switch. A further object of the
invention is the provision of such improved debouncer circuit utilizing
circuitry readily implementable as part of an integrated circuit package.
A still further object of the invention is to provide an improved
debouncer circuit having the capability for synchronizing the resulting
debounced signals to a clock signal for subsequent use with other logic
signals. It is a still further object to provide an improved debouncer
circuit which employs totally digital circuit elements for interfacing
with a single-throw switch.
According to the present invention, there is provided an improved debouncer
circuit for providing debounced, synchronously clocked digital signals
from a single-throw switch, as for instance, of the momentary contact
type. A signal which is variable between two logic levels is provided by
the switch for input to the debouncer circuitry. That input signal is
applied as one input to an EXCLUSIVE OR gate, the other input to that gate
being fed back from the Q output terminal of an output data latch having
complementary Q and Q* output terminals. The Q* output terminal of the
data latch is connected to the D input of that latch such that a clocking
signal appearing at the clock input of the data latch serves to toggle the
states of the Q and Q* output terminals. The signal appearing at either
one of the output terminals Q, Q* of the output data latch may be used as
the debounced signal provided to other circuitry, depending upon signal
polarity needs.
The output of the EXCLUSIVE OR gate is a logic 1 only when the two inputs
differ. A synchronous clock signal having a period T.sub.DB is supplied in
both its real and inverted form to effect the requisite synchronization.
Further logic including a second D-type flip-flop data latch, a NAND gate
and an AND gate are interconnected with the output of the EXCLUSIVE OR
gate and with the synchronous clock signals for providing a clocking
signal which is extended to the clock input of the output data latch. That
logic is configured such that the logic levels appearing at the output
terminals of the output data latch are toggled only if the input signal
voltage from the single-throw switch changes state and remains in the new
state for at least a capture time interval of T.sub.DB +T.sub.A, where
T.sub.A represents the variable interval between the initial change of
state of that input signal and the next-occurring synchronous clock
signal.
The output signal from the EXCLUSIVE OR gate, one phase of the synchronous
clock signal and the Q output terminal of the second data latch are each
applied as respective inputs to the NAND gate, the output of that NAND
gate serving to provide the clocking signal applied to the output data
latch. Further, the signal at the output of the EXCLUSIVE OR gate and the
Q output of the second data latch are each applied as respective inputs to
the AND gate. The output of that AND gate is extended to the data input of
the second data latch, and the other phase of the synchronous clock signal
is applied to the clock input of the second data latch to complete the
circuitry for establishing the capture time interval. A preset signal may
be extended to the present inputs of the output data latch and the second
data latch for presetting their respective output terminals prior to the
introduction of any input signals.
The debouncer circuit of the invention finds particular utility in those
applications employing a single-throw switch for signal input and
requiring synchronization of the resulting debounced digital signal.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is an architectural block diagram of a communication system in
accordance with the present invention;
FIG. 2 is a generalized schematic block diagram of the multiplex computer
comprising part of the embodiment of FIG. 1;
FIGS. 3A and 3B in combination are a more detailed schematic block diagram
of the multiplex computer of FIG. 2, with all of the circuitry of FIG. 3A
being powered in a switch-controlled manner and all of the circuitry of
FIG. 3B being continuously powered;
FIG. 4 is a schematic block diagram of a Master/Monitor Mux Controller used
in the multiplex computer;
FIG. 5 is a series of waveform illustrations A-L of particular signals
associated with the Controller illustratead in FIG. 4;
FIG. 6 is a schematic block diagram of a Remote Mux Controller used in the
system illustrated in FIG. 1;
FIG. 7 is a schematic diagram of debounce circuitry and latch circuitry
associated with the Remote Controller;
FIG. 8 is a series of waveform illustrations used in the description of the
embodiment of FIG. 7;
FIG. 9 is a schematic diagram of address input and signal output circuitry
used with integrated circuit devices employed in the embodiment of FIG. 7;
FIG. 10 is a series of waveform illustrations used in the description of
the embodiment of FIG. 9;
FIG. 11 is a flow diagram of the decision and control routine associataed
with configuring the Multiplex Controllers as Master and Monitor for
communications integrity for the system;
FIG. 12 is a flow diagram of the decision and control routine associated
with an evaluation of the integrity of the serial communications;
FIG. 13 is a flow diagram of the decision and control routine associated
with the "sleep" mode of system operation.
BEST MODE FOR CARRYING OUT THE INVENTION
There follows a detailed description of an exemplary system with which the
debounce circuit of the invention maybe employed; however, the detailed
description of the debounce circuit occurs near the middle of the
specification with reference to FIGS. 7 and 8.
FIG. 1 is an architectural block diagram of the multiplex communication
system 10 for the body electrical functions of a vehicle and incorporating
the present invention. In the interest of brevity, several abbreviations
or shorthand expressions will be used hereafter in place of the full
descriptive name or function an an element, for instance, the word
"multiplex" will often be expressed as "Mux" and a remote multiplexer will
be referred to as a "Remux". Further still, the designations for various
signals appearing on various conductors or at various ports in the system
will be represented by descriptive abbreviations. Still further, the logic
employed in the illustrated embodiment uses, in many instances, the
"active-low" state of a signal for effecting some result. Although that
"active-low" state is represented in the Drawings by a line or "bar" over
the signal expression, that same "active-low" state is represented in the
text by a * adjacent to the signal representation because of printing
limitations. The multiplex communication system 10 employs a Mux computer
12 located at a central station within an automotive vehicle for providing
control to and interacting with one or more remote multiplex (Remux)
controllers 14 positioned at various remote locations about the vehicle.
Communication between the Mux computer 12 and the Remuxes 14 is afforded
via a four wire bus 15 which includes a first wire 16 for carrying
bidirectional, serial, time division multiplexed data, a second wire 17
for conveying the serial multiplex clock (MUXCLK), a third wire 18 for
extending a +5 volt DC supply voltage to the Mux computer 12 and the
Remuxes 14 and a fourth wire 19 which serves as a signal ground (GND) for
the multiplex system 10. The five volt supply voltage and the ground may
be supplied by and referenced to the conventional 12 volt battery (not
shown) of an automotive vehicle via a 5 volt regulator 20.
Although the multiplex communications bus 15 between the Mux computer 12
and the various Remux controllers 14 might in some applications be open
ended with the Mux computer 12 being located at one end and the various
Remux controllers 14 tapping in parallel "T" connection to the conductors
16-19 along the length of the bus, in accordance with an aspect of the
present invention the bus 15 is formed as a loop which is terminated at
its opposite ends or terminals by differing portions of the Mux computer
12 to provide increased integrity and security to the multiplex
communication system 10 as will be hereinafter described. Provision of a
communication bus 15 configured as a loop controlled at each end by the
Mux computer 12 pemits detection of various anomolies which may occur in
the transfer of information, such detection being of a nature to identify
one or more breaks in the bus 15 and to further provide for maintaining
transmission integrity in the event of such line break.
The Mux computer 12 located at the central station includes a standard
microprocessor 22 operatively connected with a master Mux controller 24
and a monitor Mux controller 24'. The master Mux controller 24 (Master
Mux) and the monitor Mux controller 24' (Monitor Mux) are each formed of
custom LSI CMOS gate array circuitry and are identical in construction but
differ somewhat in operation as a function of time and control mode. One
end of the loop of multiplex bus 15 is connected to Master Mux 24 and the
other end is connected to Monitor Mux 24'. The microprocessor 22 in the
preferred embodiment is a 4 MHz Z80, such as the Mostek 3880, employing
NMOS circuitry, but it will be understood that other microprocessors are
similarly applicable. Memory 25 is also provided in conjunction with
microprocessor 22 in the Mux computer 12, and typically includes a 1K CMOS
random access memory (RAM) 26 and a 4K CMOS programmable read only memory
(EPROM) 27 shown in FIG. 2. Mux computer 12 also includes oscillator and
counter/timer circuitry, generally represented by the function block 28,
for generating the system timing signals and for providing a "sleep mode"
of operation to be described hereinafter in greater detail. Operative
interconnection between the microprocessor 22, memory 25, oscillator and
counter/timer 28 and the Master and Monitor Muxes 24, 24' is afforded by
various control lines shown later in greater detail as well as by a data
bus and an address bus, so designated, within the functional illustraton
of Mux computer 12.
All of the Remuxes 14 connected to the multiplex bus 15 are of similar
construction, each being an LSI gate array employing CMOS logic elements.
Each Remux controller 14 is provided with significant logic capacity for
"intellectual" interaction with the Mux computer 12, and typically
includes provision for 16 inputs from various vehicle switches and 16
outputs to various vehicle loads, a typical switch input being that for
on-off control of headlights and a typical output being a control signal
for turning on or turning off the headlights. It will be appreciated that
the switch inputs may derive from the need to control numerous diverse
loads and functions and similarly, that the output signals will serve to
control numerous diverse types of loads. The architecture of each Remux 14
is such that it is divided into halves, each half having eight inputs and
eight outputs and having a separate address. More specifically, one side
of a Remux 14 is designated the A side and is provided with an even
numbered address and the other side is designated the B side and is given
an odd number address which is numerically 1 greater than the A side
address. The outputs from Remuxes 14 to the various vehicle loads
typically provide low voltage control signals to various control elements
or buffers 30 which in return respond by connecting or disconnecting the
vehicle 12 volt supply to the load being controlled.
The multiplex communication system 10 employs a communications protocol
illustrated in FIG. 5B for use in the data communications between the Mux
computer 12 and the Remuxes 14. This data protocol is intended to enhance
the integrity of the communications system through an efficient detection
of communication errors and/or anomolies. A thorough description of this
data protocol is contained in U.S. application Ser. No. 469,591 for
Vehicle Multiplex System Having Protocol/Format for Secure Communication
Transactions filed Feb. 24, 1983 by William Floyd and assigned to the same
assignee as the present application, and is incorporated herein by
reference. Briefly, each communication transaction on the Mux data line 16
of multiplex bus 15 includes seven characters or bytes of eight bits each,
the first byte being a sync byte, the following three bytes comprising a
command message from the master controller 24 consisting of an address
byte, a command byte and a CRC error detect byte and the final three bytes
comprising a reply message from a Remux 14 consisting of an address byte,
a response byte and a CRC error detect byte. Although the system 10 as
presently configured has the potential for controlling as many as 128
Remuxes 14, each having two separate addresses, it will be understood that
usually far fewer Remuxes 14 are actually required, only two being
illustrated in the FIG. 1 embodiment.
Referring briefly to FIGS. 2, 3A and 3B, the system clock (SYSCLK) for
controlling the timing of the microprocessor 22 and various other elements
of the Mux computer 12 is typically of 2.5 MHz and is provided by an RC
oscillator 28 of conventional design. Further, a similar type of RC
oscillator provides a 50 KHz source 30 which is divided by two in the
initial stage of a multistage binary counter 32 to provide a 25 KHz clock
signal which is used as the multiplex clock (MUXCLK). Inasmuch as the
serial Mux data appearing on multiplex bus 15 is clocked at a 25 KHz rate,
the period of each bit will typically be 0.04 ms and the period of an
eight-bit byte is 0.32 ms. Interactions between the microprocessor 22, its
program stored in EPROM or PROM 27, the data stored in RAM 26, and the
Master and Monitor Muxes 24, 24' is conducted at a rate determined by
SYSCLK. Interaction between the microprocessor 22 and the memory elements
26 and 27 is determined by conventional decode control logic 34 which
additionally includes timer decode logic for providing certain control
signals to timer circuitry and power control switch circuitry generally
represented by the blocks designated 31 and 35, respectively in FIG. 2 to
be described hereinafter in greater detail. The processor 22 is interrupt
driven, a nonmaskable interrupt (NMI)* being provided by the timer 31 at
approximately 20 ms intervals. The hardware timer 31 includes two,
eight-stage, divide-by-256 counters, 32 and 33, respectively of FIG. 3B. A
timing signal occurring at 20 ms intervals from the timer 31 is applied to
pulse generating circuitry, generally designated 36 in FIG. 2 for
providing the NMI* signal. Additionally, upon initial powering-up of the
multiplex system 10, as by connecting of the vehicle's battery cable, a
conventional power up reset signal PUR.sub.1 is generated by conventional
circuitry represented by block 37. This PUR.sub.1 signal may also be
applied to the pulse generating circuitry 36.
As is evident in FIGS. 2, 3A, and 3B, processor 22 utilizes eight
bidirectional data lines D.sub.0 -D.sub.7 for the parallel output and
input of data to the memory elements 26, 27 and the Master and Monitor
Muxes 24, 24'. The processor also includes 16 address lines A.sub.0
-A.sub.15 for providing addressing signals to the memories 26, 27 and
Master and Monitor Muxes 24, 24', as well as to the decode control logic
24. The data bus between processor 22 and the Master and Monitor
multiplexers 24, 24' is designated 40 and the corresponding address bus
between those elements is designated 42 and consists of A.sub.0 -A.sub.9.
Five further signal lines are provided at the processor 22 and at the
Master and Monitor multiplexers 24, 24', and are designated RD*, WR*,
IORQ*, M1*, and INT*. The RD* signal is issued by processor 22 when it
wishes to read data from memory 25 or an I/O device such as the
multiplexers, 24, 24'. Depending on which is addressed by processor 22,
one or the other of the multiplexers 24, 24' is issued the RD* signal to
gate data onto the data bus 40 from multiplexes 24, 24'. The WR* signal
provided by processor 22 indicates that the data bus 40 holds valid data
to be stored in the addressed memory 26, 27 or I/O device multiplexers 24,
24'. The IORQ* signal indicates that the address bus 42 contains a valid
I/O address for an I/O read or write operation. This signal is also
generated with an M1* signal when an interrupt is being acknowledged to
indicate that an interrupt response vector can be placed on data bus 40.
The M1* signal indicates that the current processor cycle is the OP-Code
Fetch cycle of an instruction execution, and it also occurs with IORQ*, as
mentioned, to indicate an interrupt acknowledge cycle. The INT* signal is
one generated by a multiplexer operating in its Master Mode, as Master
Multiplexer 24, and is directed to processor 22 when an interrupt is being
requested. This request is honored by processor 22 at the end of the
current instruction being executed by the processor.
The processor 22 issues a further control signal designated MREQ* which is
extended to the RAM and EPROM decoding circuitry and to the MNI* pulse
generator for selecting either ROM or RAM when the address holds a valid
address for a Memory Read or Memory Write operation, and enabling the NMI*
generator to provide a pulse for the NMI* input.
Referring to FIG. 3B, it will be noted that Master and Monitor Multiplexers
24 and 24' each include address input lines ADDCMP 1-7 for fixing or
hardwiring their respective addresses. With respect to Master Monitor 24
it will be noted that all of the ADDCMP 1-7 inputs are tied to ground
(logic 0) except for ADDACP 4 which is at +5 volts (logic 1). A similar
situation exists with Monitor Multiplexer 24' except that the input ADDCMP
4 is a logic 0 and input ADDCMP 5 is a logic 1. Accordingly, the Master
and Monitor Muxes 24, 24' are separately identified and identifiable in
their respective communications with processor 22.
Each of the Master and Monitor Mux modules 24, 24' also includes an input
designated MR which receives a signal designated PUR.sub.2 obtained in a
manner to be hereinafter described and which effects a resetting
initialization of the internal control registers and timing of the
respective Muxes 24, 24'.
At this juncture it is appropriate to further consider the operating
protocol of the multiplex system 10 particularly as regards serial data
multiplex transactions between the Mux computer 12 and the Remuxes 14. In
accordance with the routine of programmed instructions contained in ROM
27, the processor 22 scans the various Remuxes firstly to establish what,
if any, input switches have been actuated, and secondly to effect the
requisite output control action to the appropriate loads. To effect this
control, the processor 22, which typically provides and receives operating
addresses and data in a parallel manner, utilizes the Master Multiplexer
24 to convert the address and command issued to the respective Remuxes 14
into a serialized data format and to reconvert the serialized address and
response data issued by the Remuxes 14 into a parallel format for
transmission on the parallel data bus 40 to processor 22. As mentioned
earlier, a typical transaction between the Mux computer 12 and a Remux 14
includes, as illustrated in the trace of FIG. 5B, the issuance of a sync
byte followed by an address byte, a command byte and an error check (CRC)
byte in the message sent from the Master Mux 24 to a particular Remux 14.
Subsequently the addressed Remux 4 will, or should, reply on Mux data line
16 with an address byte, a response byte and an error check (CRC) byte.
The address byte sent by the Master Mux 24 contains the address of a
selected half of one of the Remuxes 14. The command byte instructs the
addressed Remux to respond with various input signals which it may have
received by the actuation of outside switches and/or to provide output
control signals to the output load devices connected to that particular
half of the Remux. A cyclical redundancy error checking technique utilizes
the address and command bytes for generating an error check byte which is
transmitted to the addressed Remux. The Remux 14 which responds is
presumably that which was addressed by Master Mux 24 and the response is
initiated with an address byte which indicates the address of the
particular responding Remux. That byte is followed by a response byte
which indicates the response taken by the particular Remux to the recieved
command message; typically revealing the status of various input switches
and actuation of output loads. In this regard, the status of switch inputs
and/or output loads is typically determined by sampling latched switch
inputs and actuation responses of load outputs. The response byte will
typically also include an indication of whether or not the particular
Remux, having done its own error checking of the incoming message from
Master Mux 24, "agrees" with its error check byte. Finally, the error
check byte sent by the Remux 14 will have been calculated using a CRC
technique using its Address and Response in reply message. The multiplexer
does its own error checking on the Remux Reply. Following each such
transaction there may or may not be a period of bus latency in which all
"ones" are written while a further instruction is awaited from processor
22.
Referring now to FIG. 4, the Master and Monitor Muxes 24, 24' are
considered in greater detail. Because both are of identical architecture,
they are discussed and illustrated as one in FIG. 4, though they are
capable of functioning differently from one another in accordance with the
invention. Accordingly, the discussion will first be from the standpoint
of the Master Mux 24 and subsequently the Monitor Mux 24'. Further in FIG.
1 the bus 15 and its MUX DATA line 16 and MUXCLK line 17 are each shown
with arrows at both ends, the solid arrowheads depicting the general flow
in the presently discussed and illustrated configuration, and the dotted
arrowheads depicting the reversed configuration.
When power is initially applied to the Muxes 24 and 24', their initial
states will be that of a monitor. This means they are both in the receiver
or listener mode and are searching for the SYNC byte on the serial Mux
data line 16. To convert Mux 24 to the Master status, its eight bit
control register 46 must be programmed. This is accomplished by processor
22 addressing the Mux 24 using the Address Bus 42 and comparing the
address in the Address Compare Logic 48 with the device's address
established at the inputs ADDCMP 1-7. Assuming further that the A.sub.0
bit of the address sent is a 1, a CNTLCOMP signal is issued to the control
register 46 such that when the processor 22 executes a write operation,
WR, control data will enter register 46 from data bus 40. The programming
of the control register 46 for the Master Multiplex function includes
setting bit number 4 to a 1 to reset the internal logic in the Mux module.
Once completed, bit number 4 automatically resets itself. Bit number 2 of
register 46 is set to a 1 to enable the next byte on Data Bus 40 to be
written into the Vector Address Register 50. Once completed bit number 2
automatically resets itself. Bits number 0, 1 and 3 must be set to 1 for
the Mux to operate as a master. Specifically, if bit number 0 is a 1, the
device is a master, otherwise it is a monitor. With bit number 1 as a 1,
the Mux clock, MUXCLK, is transmitted on line 17 of bus 15. With bit
number 3 as a 1, the Interrupt Logic 52 is enabled. Bit numbers 5, 6 and 7
may be programmed to any state since they are not used.
Following programming of Control Register 46 such that the device 24 will
act as a Master Mux, it is again addressed by processor 22 and the
multiplexing operation is initiated by writing the appropriate data byte
(Address byte) into the Multiplex Register 54. The address comparison at
logic 48 for entering data in Multiplex Register 54 is achieved when
A.sub.0 =a logic 0, and data is entered in the register during a write,
WR, operation. Then, once the Address byte is written into the Multiplex
Register 54, Master Mux 24 will start transmitting the SYNC character or
byte (00010110) on the serial bus 16. The SYNC byte is derived from a SYNC
Register 56. Synchronization of the SYNC byte and the subsequent data
bytes transmitted by Master Mux 24 is effected by a conventional
synchronization circuit 58 receiving a synchronization control signal
SYNC, from counter logic 60 which responds to the 25 KHz Mux CLK for
providing the appropriate phasing to the SYNC signal. Once the SYNC Byte
is finished being transmitted on data line 16, the Address byte stored in
register 54 will be converted from parallel to serial by register 62 and
is then automatically appended to the SYNC byte on the serial bus via
synchronizing circuitry 58. An interrupt, INT*, is then generated.
The interrupt signal INT* is requesting that the processor 22 stop its
existing action and service the MUX 24. A TINTRQ signal from the counter
logic 60 is applied to Interrupt Decision logic 64 and being extended
therefrom as an interrupt request signal to the Interrupt Register and
Logic 52 for extension as signal INT to the processor 22. Sometime after
an interrupt is requested by the Master Mux 24, the processor 22 will send
out an "interrupt acknowledge" (MI* and IORQ*). During this time, the
Interrupt Logic 52 of Master Mux 24 will determine the highest priority
device which is requesting an interrupt. This is simply the device with
its interrupt enable input, IEI, at a logic 1 and its interrupt enable
output, IEO, at a logic 0. It will be noted in FIG. 3B that the IEI input
of Master Mux 24 is tied to +5 volt and its IEO output is tied to the IEI
input of the Monitor Mux 24'. The Interrupt Logic 52 is such that when IEI
is a logic 1, no other devices of higher priority are being serviced by an
interrupt service routine from the processor 22. Additionally, the IEO
signal from the Interrupt Logic 52 will be a logic 1 only if the IEI input
to that Mux is a logic 1 and the processor 22 is not servicing an
interrupt from that multiplexer. Thus, when the processor 22 is servicing
an interrupt from that multiplexer, its IEO signal is a logic 0 and will
serve to place the IEI inputs of other multiplexers to which it is
connected to a logic 0, thereby making them subservient in the priority of
interrupt servicing. To ensure that the interrupt priority daisy chain is
stabilized, Multiplex devices are inhibited from changing their interrupt
request status when M1* is active (0). The highest priority device places
the contents of its Interrupt Vector Address Register 50 onto the data bus
40 during "interrupt acknowledge". After an interrupt by the Master
Multiplex is acknowledged, that multiplexer is "under service". The IEO of
this device will remain low until a return from interrupt instruction
(RETI=ED.sub.H 4D.sub.H) is executed while the IEI of the device is a
logic 1. If an interrupt request is not acknowledged, IEO will be forced
high for one M1* cycle after the multiplex 24 decodes the Op code
"ED.sub.H ". This action guarantees that the two bytes RET 1 instruction
is decoded by the proper Mux device.
When the processor 22 receives the interrupt, it has one byte time (0.32
ms) in which to write the Command byte into the Multiplex Register 54. If
this time has elapsed before data is written into the register 54, the
data on the serial bus 16 following the Address byte will be nonvalid. As
was the case with the Address byte, the Command byte will be transferred
from register 54 through parallel to serial converter register 62 for
output to the serial data line 16 via the data multiplexing sync circuit
58, the CRC data Mux gate 66 and the transmitter circuitry 68.
As the serial Address and Command data bytes are being read from register
62 onto the serial data line 16, they are also being provided on the line
designated "SDATA#2" to an input of an EXCLUSIVE OR gate 70 having its
output connected to an input stage of CRC calculator register 72. The
other input to the EXCLUSIVE OR gate 70 is provided by a selected one of
the output stages of the CRC register 72 to perform the CRC calculation
function in accordance with the description provided in the aforementioned
application Ser. No. 469,591. Immediately following transmission of the
Command byte, the CRC byte will have been generated in register 72 and is
serially read therefrom and through the CRC Data Mux circuit 66 which has
been enabled by a CRC word select signal CWS from the counter logic 60.
Upon completing the transmit mode, the Master Mux 24 automatically switches
into the receiver mode. In the receiver mode, the Remux Address byte will
be the first character to be received, after which an interrupt will be
generated to signal the processor 22 that it is time to read that byte.
Once again the processor has 0.32 ms in which to read the byte, after
which the byte is no longer valid. The data being received from line 16 by
Master Mux 24 first enters through receive buffering circuitry 74 and is
gated through logic circuitry 76 to the serial to parallel register 62. A
transmit/receive control signal TNRECNTL applied to gate circuit 76
provides for the received data, R DATA, to be passed to serial to parallel
register 62 and also provides that that data be extended to an input of
the EXCLUSIVE OR 70 for use in the calculation of a CRC byte during the
receive mode.
In the receive mode, the second byte will be the Remux response byte and it
will be received in the same manner as the remote address byte. It too
will signal the processor 22 with an interrupt indicating that valid data
can then be read. The final byte received by Master Mux 24 will be the
Remux's CRC byte. This byte will be compared to the byte generated by the
CRC calculator 72 from the incoming data stream during the receive mode.
If the two bytes compare, bit number 0 in the Master Muxes status register
78 will be a 0, whereas if the two CRC bytes do not compare bit number 0
in register 78 will be a 1. Also, an interrupt is again generated to
signal the processor 22 that the status register should be read. Reading
the status register 78 serves to reset that register. In addition to the
state of bit number 0 in status register 78 serving to indicate the
correctness or incorrectness of the CRC from the Remux, the state of bit
number 1 will be indicative of operation in the transmit or the receive
mode, the state of bit number 2 will be indicative of the correctness or
incorrectness of the CRC comparison if the device is operating in the
monitor mode as will be discussed hereinafter. The state of bit number 3
signifies whether or not the Master Mux and Remux addresses compare when
the device is operating in the monitor mode as will be described
hereinafter and the state of bit number 4 is used to signify when a
transaction has been completed.
When the status register 78 has been read and reset, the Master Mux 24 will
switch back to the transmit mode and will send ones onto the serial bus
16; thus waiting for a write, WR*, from the processor 22 to initiate
another transaction.
Brief reference to the timing diagram provided by FIGS. 5A-L further
correlates the timing of the above-described functions with the various
parts of a complete transaction performed by Master Mux 24. It will be
noticed in 5K that a single interrupt is generated during the transmit
mode, whereas three separate interrupts are generated during the receive
mode. It will also be noticed that the control signal DLOAD is 5E for
loading parallel data into the parallel to serial register 62 occurs at
the beginning of the address, command and CRC bytes respectively during
the transmission mode, whereas that function to convert from serial to
parallel occurs at the end of the address, response and CRC bytes during
the receive mode. The determination of whether or not the CRC byte
received by Master Mux 24 was correct is determined by the signal CRC OK?
appearing in 5I at the end of the CRC byte appearing at the end of the
transaction. A Master Address/Receive Address comparison signal M/RCOMP?
occurs at the end of the receipt of the Remux address during the receive
mode of the transaction; however, this function is performed only by
Monitor Mux 24' as will be discussed hereinafter.
Referring now the operation of a multiplex controller in its monitor mode,
as represented by Monitor Mux 24', the monitor mode may be attained either
upon power-up initialization or by writing a 0 into bit numbers 0 and 3
of the control register 46. In this mode the multiplexer functions only as
a receiver or listener, and interrupts to the processor 22 are never
generated. In such monitor mode the INT* is tri-state. After establishing
a particular Mux as a monitor 24', an output line designated bus listen
control BUSLCNTL from the bit number 0 position of control register 46
serves to control Master/Monitor select circuitry 80 for generating a
control or gating signal MONLY which is a 1 when the device is to operate
as a Master Mux and is a 0 when it is to operate as a monitor. The MONLY
control signal is extended to those portions of the Master/Monitor Mux
circuitry which are to provide different modes of operation depending upon
whether the chip is configured as a master or as a monitor. When
configured as a Monitor Mux 24', the device operates only as a receiver
and therefore is in the "sync search" state awaiting receipt of a Sync
byte at the "downstream" end or terminal of the serial data line 16. When
the Sync byte is received, it is recognized by Sync Detect Logic 63 and
the Monitor Mux is initalized for enabling the following three bytes on
the serial bus to be acknowledged. The first byte received after the Sync
byte is the Remux address transmitted by the Master Mux. This byte is
stored in the data buffer, MUX Data Register 54, for comparison later with
the address byte sent by the responding Remux 14. Further, that first byte
is gated through the CRC data Mux 76 and EXCLUSIVE OR gate 70 to the CRC
calculator 72. The next byte received is the command from the Master Mux
24 and it also is gated through CRC data Mux 76 and EXCLUSIVE OR 70 into
the CRC calculator 72 for determining a CRC byte value at the monitor. The
third byte received by monitor 24' will be the Master's CRC. This CRC byte
is also conducted through the CRC data Mux 76 and the EXCLUSIVE OR 70 to
the CRC checker 72 to determine whether or not the CRC bytes compare. If
the results are the same, bit number 2 in the status register 78 will be
set to a 0 and if not, a 1 will be placed in bit number 2 of that
register. After this operation, the CRC calculator 72 is automatically
cleared.
The fourth byte received by Monitor Mux 24' is the address byte sent by a
responding Remux 14. This byte is compared to the Address byte previously
sent by Master Mux 24 and presently stored in Mux data register 54. The
comparison of the two address bytes occurs in Address Compare Logic 84
which is active only if the Mux chip is acting as a monitor 23'. If the
two address bytes compare, bit number 3 of the Status Register 78 will be
set to 0 and if not, a 1 will be place in bit number 3 of that register.
Byte 4 received by Monitor Mux 24' is also passed through CRC data Mux 76
and EXCLUSIVE OR gate 70 into the CRC calculator 72 for use in determining
a CRC byte. The fifth byte received by Monitor Mux 24' is the Response
byte issued by the responding Remux 14. This response byte is directed
through CRC data Mux circuit 76 and EXCLUSIVE OR gate 70 to the CRC
calculator for determination of the CRC error byte.
The sixth byte received by Monitor Mux 24' is the CRC byte sent by the
responding Remux 14. This byte is also directed through CRC data Mux 76
and the EXCLUSIVE OR gate 70 for comparative combination with the CRC byte
then stored in register 72. In the event the CRC byte transmitted by the
Remux compares with that calculated in the Monitor Mux 14, a 0 will be set
in the bit number 0 position of the status register 78, but if the bytes
do not compare, a 1 will be placed in the bit number 0 position of the
status register. Upon completion of this transaction, the SYNC search mode
will be restored; thus enabling a new operation to begin.
Although the Monitor Mux 24' is not capable of generating an interrupt to
the processor 22, the processor will instead interrogate the Monitor Mux
24' followin each transaction to ascertain whether or not the address and
CRC checks performed by the monitor indicate accuracy, integrity and
consistency in the transmissions between the Master Mux 24 and Remux 14.
In the event errors are reflected by one or more of these checks, the
processor 22 is capable of taking various forms of corrective action.
Prior to a further discussion of the centralized control of the
multiplexing system 10 by Mux computer 12, the circuitry of a
representative Remux 14 will be described in somewhat greater detail with
reference to FIGS. 1 and 6. Firstly referring to FIG. 6, a representative
Remux 14 is illustrated in functional block diagrammatic form. The Remuxes
14 are provided by LSI gate array logic configured to provide the requiste
functions discussed herein. Each Remux 14 is connected with the Mux bus
loop 15 via parallel "T" connections with the respective four wires 16-19
of that bus. The provision of +5 volts and ground is not shown but is
implied. The bidirectional data line connecting Remux 14 with the Mux data
line is designated 16' and the line connecting the Remux with the MUXCLK
line 17 is designated 17'. Appropriate circuitry 120 is located in line
17' for buffering the received MUXCLK. Similarly, in line 16' there is
provided Receive buffering circuitry 121 and Transmit buffering circuitry
122 connected in complementary relationship. The incoming data on line 16'
and the MUXCLK on line 17' are supplied as inputs to an eight bit
serial-to-parallel and parallel-to-serial shift register 125 which is
responsible for providing the appropriate conversions of data from one
form to the other in response to an appropriate control signal CRTL. As
used in the description of FIG. 6, the control signals CRTL are provided
by control logic 128 and may provide a variety of control functions. The
following discussion is intended to reveal the ch | | |
