A bit error measuring device for modem device, comprises; a control code detecting unit for detecting a flow control code set in an input signal from the modem device, and for masking the flow control code, a bit error measuring unit for measuring bit errors in the input signal of which the flow control code is masked, a clock controlling unit for controlling an output of a clock signal by the flow control code, and a test pattern transmitting unit for transmitting a test pattern signal by synchronizing with the clock signal when clock pulses of the clock signal are outputted from the clock signal controlling unit, and for stopping a transmission of the test pattern signal when the clock pulses of the clock signal are not outputted from the clock signal controlling unit.

For imitating periodic signals occurring in digital transmission systems during some operating conditions in view of the multiplex structure a word generator is proposed which includes a read-only memory from which during a test signal cycle only 4116 permutations are successively read out of a total of 65,536 possible word sizes and permutations of e.g. a 16-bit word. The remaining 61,420 permutations are generated by shifting bit-by-bit the entire packet of continuous signals so that in case of a fixed 16 bit pattern the packet starts at a different bit position during each successive cycle and after 16 cycles all 16 bit positions occur as begin state. The shift is caused by a framing bit sequence which determines the test signal cycle and whose length is aliquant to n=16.

A test pattern generator includes: an algorithmic pattern generator, a sequential pattern generator, a selector for selecting one of an algorithmic pattern and a sequential pattern for use with a specified pin of an object device to be tested; and a pattern controller for controlling the selector, whereby data to be supplied to a pin or pin block can be assigned in real time by the pattern controller.

A semiconductor test device including a function test algorithmic pattern generator which comprises: an ALU unit with shift-in function for conducting a predetermined arithmetical and logical operation against the base data or the output of an ALU output register; the ALU output register being designed to store the output of the ALU and output a function test algorithmic pattern; and a parity detection circuit which conducts a parity detection against an arbitrary group of bits of the ALU output register, and the detection output is input into a shift-in input of the ALU.

In automatic test equipment the logical levels on certain of the test pins are set to 0 and 1 by corresponding flip-flops included in respective I/O logic circuits. The states of the flip-flops (as well as other factors) are controlled by commands read out of a control RAM which is of sufficient width to provide a 4-bit command on lines for each logic circuit. The available commands include NOP commands and change commands which toggle the states of the corresponding flip-flops. A relatively small number of addresses of the control RAM have change commands entered in correspondence with selected ones of the pins. By repeatedly reading out the commands in these addresses in a non-cyclic sequence it is possible to generate a succession of different states of the flip-flops in the logic, which succession is much longer than the number of addresses of the control RAM which are utilized. Apparatus for establishing the correct addressing sequence is described.