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Voltage balancing circuit for memory systems
   
Document Number
US Patent 4555776
Issued Date
November 26, 1985
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Abstract
A voltage balancing circuit, particularly suitable for bipolar memory arrays producing small signals, is provided which includes first and second conductive lines, a point of reference potential, a first device disposed between the first conductive line and the point of reference potential, a second device disposed between the second conductive line and the point of reference potential, first and second transistors, first means for coupling the first line through the first transistor to the second line, second means for coupling the second line through the second transistor to the first line, and means for supplying substantially equal signals to the control electrodes of the first and second transistors. When used in a memory array, the conductive lines are the bit/sense lines, the point of reference potential is a bit/sense line reference voltage and the equal signals for the control electrodes of the transistors are provided in response to a signal from a bit decoder.
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Voltage balancing circuit for memory systems - US Patent 4555776 Drawing
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Number of Claims:
23
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Published
November 26, 1985
Application Number
06/369,970
Filed
April 19, 1982
US Classification
365/202   365/154 365/179
Int'l Classification
G11C   11/414   (20060101)   G11C   11/416   (20060101)  
Attorney/Law Firm
USPTO Field of Search
365/154   365/155   365/179   365/190   365/203   365/174   365/202   307/264   307/299A  
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Description
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