A semiconductor dynamic read/write memory device using one-transistor storage cells and balanced bit lines employs a differential sense amplifier having dual sets of transistors for both the N-channel and P-channel transistor pairs in a CMOS flip-flop circuit. One set of P and N channel transistors is cross-coupled in the conventional manner, and the other set is cross-coupled by way of series transistors which are shut off for write operations, bypassing static loads for write.
In a CMOS ROM memory arrangement, the use of the least significant column address bit to perform the dual function of even/odd bit line select and the disconnection of the selected bit line (17' and 17") from the sense amplifier (66) driven, in order to reduce its capacitive load, prior to the time of latching the information into the sense amplifier (66).
A general purpose sense amplifier, suited for memory and level shifting applications, is provided. The present invention provides a high input impedence for less loading of bit line voltages, wherein operation is relatively insensitive to capacitive mismatches on input bit line pairs. Inherent in the high input impedence design is the built-in isolation between input and output circuitry. The present invention also provides a full rail to rail separation of the output bit line voltages without requiring additional pull-up or pull-down circuitry. The present invention also provides a single strobing input for activating and deactivating the sense amplifier. The present invention also provides minimal circuitry with high speed characteristics and low power dissipation.
A single-event upset tolerant sense latch circuit for sense amplifiers is disclosed. The single-event upset tolerant sense latch circuit includes a first set of isolation transistors, a second set of isolation transistors, a first set of dual-path inverters, a second set of dual-path inverters, and an isolation transistor. The first set of isolation transistors is coupled to a first bitline, and the second set of isolation transistors is coupled to a second bitline. The second bitline is complementary to the first bitline. The first set of dual-path inverters is coupled to the first set of isolation transistors, and the first set of dual-path inverters includes a first transistor connected to a second transistor in series along with a third transistor connected to a fourth transistor in series. The second set of dual-path inverters is coupled to the second set of isolation transistors, and the second set of dual-path inverters includes a fifth transistor connected to a sixth transistor in series along with a seventh transistor connected to an eighth transistor in series. The isolation transistor couples the first and second sets of dual-path inverters to ground.
An integrated circuit having first connections, a first memory cell, first and second prechargers, and first and second data transmission devices. The first connections have a dual-rail signal applied thereto. The first memory cell is connected to the first connections and buffer-stores the dual-rail signal applied to the first connections. The first precharger precharges first lines, which are connected to the first connections. The first data transmission device, which forwards the dual-rail signal stored in the first memory cell to second connections, which are connected to a second memory cell which transmits the dual-rail signal to the first connections again using the second data transmission device. The second precharger precharges second lines, which are connected to the second connections.
An integrated circuit with a memory, includes a matrix of memory cells and sense amplifiers which are coupled thereto, with the inputs of the sense amplifiers being connected to one another and the outputs of the sense amplifiers being connected to one another via a read bus. During the reading of information from a memory cell, the sense amplifiers are simultaneously activated. As a result, the access time for reading information from a a memory cell remains substantially constant when the number of memory columns to be connected in parallel is changed. The dimensioning of the sense amplifiers may remain the same when the number of memory columns is changed, so that dimensioning need be performed only once. This results in a saving as regards time and costs.
