An expansible FIFO memory device to which additional memory stages having the same internal memory structure may be connected to form a multistage memory of increased memory storage capacity, uses a basic control circuit which is applicable to all of the added memory stages. The respective memory stages are connected in parallel such that only one memory stage is operable at one time instant in performing a data write or a data read operation. As a memory stage is completely filled with data written thereinto or conversely is completely emptied from the readout of data therefrom, the control circuit common to all of the memory stages provides appropriate signals indicative of the full condition of the memory stage in a data write operation and of the empty condition of the memory stage in a data read operation which signals are communicated to the next memory stage for activation thereof in a continuation of the data write or data read operation. Memory capacity of the expansible FIFO memory device may be thereby increased by adding memory stages thereto without complicating the control circuit and increasing the circuit components thereof.

Disclosed is a three-dimensional display system that utilizes a host processor for performing geometric transformations and a local display processor for processing the user-supplied information which defines the object to be displayed. The display processor creates image data defining the location, color and intensity of each point of the overall image. This display processor processes and stores depth data which defines the corresponding depth relationships of the image points at each location of the overall image with the depth data being stored in a depth buffer, which is part of the display processor. The depth buffer is a two port memory device with one port being a random access port and the other being a serial access port. The display processor pieplines depth buffering operations by loading a row of data from the depth buffer into a shift register and then reading (a Read operation) the relevant pixel data through the serial access port which is connected to the shift register. The display processor then performs the Compare operation between the depth of the new pixel data and the depth of the old pixel data and if appropriate, will perform a Conditional Write operation o=f the new pixel data. The Write operation is performed through the random access port. As a result, the serial access port can continually be used for Read operations during each and every clock cycle, and the random access port can be used for Conditional Write operations during each consecutive clock cycle as well.

An image reception/reproduction apparatus for reproducing an image from image information received from a transmission medium or a recording medium, comprises at least two frame memory means consisting of serial port random access memories, and memory control means for writing, in the other frame memory means, a signal read out from one frame memory means through a serial port at a video rate, wherein all contents of one frame memory can be copied to the other frame memory within a one-frame period. Even if the reception image is partially updated, an image updated within a period obtained by adding a one-frame intermemory copy period to a period required for transmitting the updated portion can be obtained.

The present invention is directed to a picture processing apparatus for painting a picture memory of a CRT display unit or similar apparatus by paint data. In accordance with this picture processing apparatus, a dual-port memory (4) is used as a frame buffer for storing picture information. In order to store paint information in a memory cell array (7), the information is internally transferred from predetermined storage circuit (9) via a data register (8) having a serial input function. The number of times the dual-port memory (4) is accessed from the processor (1) is greatly reduced so that the burden on the processor (1) can be alleviated. It is also possible to shorten the time required for the paint information to be stored in the memory cell array (7).

A peripheral apparatus for image memories can communicate image data with a memory assembly having n blocks of a standard-type DRAM, whether the DRAM is for a page mode or for a nibble mode type operation. The apparatus comprises a read data processing unit sending the data of a selected one among n pixels read from the DRAM blocks in parallel to an external image/graphics processor, a write data processing unit modifying the image data taken thereinto and writing the modified data into the DRAM blocks, a feedback data processing unit writing the image data now on displaying into the DRAM blocks after a desired processing again, a display data processing unit sending the data read from the DRAM blocks to a monitor for display and to the external processor for the feedback processing, and a control unit furnishing control signals to those processing units in response to instructions from the external processer.